Processing apparatus and processing method

Patent metadata

Field	Value
Publication number	US-11720353-B2
Application number	US-201916697637-A
Country	US
Kind code	B2
Filing date	Nov 27, 2019
Priority date	Apr 19, 2017
Publication date	Aug 8, 2023
Grant date	Aug 8, 2023

Abstract

The present disclosure provides a processing device and method. The device includes: an input/output module, a controller module, a computing module, and a storage module. The input/output module is configured to store and transmit input and output data; the controller module is configured to decode a computation instruction into a control signal to control other modules to perform operation; the computing module is configured to perform four arithmetic operation, logical operation, shift operation, and complement operation on data; and the storage module is configured to temporarily store instructions and data. The present disclosure can execute a composite scalar instruction accurately and efficiently.

First claim

What is claimed is:

1. A device supporting a composite scalar instruction comprising:
a storage circuit configured to store a composite scalar instruction and multiple types of data, wherein the multiple types of data are respectively stored in different addresses in the storage circuit in accordance with the types;
a controller circuit configured to read the composite scalar instruction from the storage circuit and decode the composite scalar instruction into a control signal; and
a computing circuit configured to:
receive the control signal from the controller circuit,
read data from the storage circuit,
determine a data type according to an address of the read data, and
process the read data,

wherein the composite scalar instruction is an instruction that combines a floating-point instruction and a fixed-point instruction,
wherein the composite scalar instruction includes an opcode field, an operand address field, and a destination address field,
wherein a data type is determined according to an address in an address field of the operand upon computation,
wherein an opcode stored in the opcode field is used for distinguishing operations of different types,
wherein the operand address field is used for distinguishing types of operands, and
wherein the target address field is an address where a computation result is stored.

2. The device supporting a composite scalar instruction of claim 1 ,
wherein the data stored in the storage circuit includes original data and intermediate data,
wherein the device further includes an input/output circuit configured to transmit the original data and the composite scalar instruction to the storage circuit, and
wherein the computing circuit is configured to store an intermediate result of computation in the storage circuit, and transmit a final computation result to the input/output circuit.

3. The device supporting a composite scalar instruction of claim 1 ,
wherein the different types of data include floating-point data and fixed-point data,
wherein the storage circuit includes a register file, RAM, and/or ROM, and
wherein the different addresses include different RAM address and/or different register numbers.

4. The device supporting a composite scalar instruction of claim 3 , wherein the computing circuit is configured to determine whether data read by the computing circuit is floating-point data or fixed-point data according to a RAM address or a register number associated with the data.

5. A composite scalar instruction, comprising:
an opcode field, an operand address field, and a destination address field,
wherein an opcode stored in the opcode field indicates operations of different types,
wherein the operand address field indicates types of operands, and
wherein the target address field is an address where a computation result is stored,
wherein the composite scalar instruction is an instruction that combines a floating-point instruction and a fixed-point instruction,
wherein a data type is determined according to an address in an address field of the operand upon computation,
wherein an opcode stored in the opcode field is used for distinguishing operations of different types,
wherein the operand address field is used for distinguishing types of operands, and
wherein the target address field is an address where a computation result is stored.

6. The composite scalar instruction of claim 5 , wherein
the operand address field includes a RAM address, a register number, or an immediate operand, and
the target address field includes a RAM address and a register number.

7. The composite scalar instruction of claim 5 , wherein
when multiple addressing modes are used for reading data, the composite scalar instruction further includes a flag bit for determining the addressing modes, and
the multiple addressing modes include register addressing, register indirect addressing, RAM addressing, and immediate operand addressing.

8. A method for supporting a composite scalar instruction comprising:
storing, by a storage circuit, a composite scalar instruction and multiple types of data, wherein the multiple types of data are respectively stored in different addresses in the storage circuit in accordance with the types;
reading, by a controller circuit, the composite scalar instruction from the storage circuit;
decoding, by the controller circuit, the composite scalar instruction into a control signal;
receiving, by a computing circuit, the control signal from the controller circuit;
reading, by the computing circuit, data from the storage circuit;
determining, by the computing circuit, a data type according to an address of the read data; and
processing by the computing circuit, the read data.

9. The method of claim 8 , wherein the data stored in the storage circuit includes original data and intermediate data.

10. The method of claim 9 , further comprising:
transmitting, by an input/output circuit, the original data and the composite scalar instruction to the storage circuit;
storing, by the computing circuit, an intermediate result of computation in the storage circuit; and
transmitting, by the computing circuit, a final computation result to the input/output circuit.

11. The method of claim 8 ,
wherein the composite scalar instruction is an instruction that combines a floating-point instruction and a fixed-point instruction,
wherein the composite scalar instruction includes an opcode field, an operand address field, and a destination address field,
wherein a data type is determined according to an address in an address field of the operand upon computation,
wherein an opcode stored in the opcode field is used for distinguishing operations of different types,
wherein the operand address field is used for distinguishing types of operands, and
wherein the target address field is an address where a computation result is stored.

12. The method of claim 8 ,
wherein the different types of data include floating-point data and fixed-point data,
wherein the storage circuit includes a register file, RAM, and/or ROM, and
wherein the different addresses include different RAM address and/or different register numbers.

13. The method of claim 12 , further comprising:
determining, by the computing circuit, whether data read by the computing circuit is floating-point data or fixed-point data according to a RAM address or a register number associated with the data.

Assignees

• Shanghai Cambricon Inf Tech Co Ltd

Inventors

• Liu Shaoli
• Luo Yuzhe
• Guo Qi
• Chen Tianshi

Classifications

• G06N3/0495

  Quantised networks; Sparse networks; Compressed networks · CPC title

• G06N3/0464

  Convolutional networks [CNN, ConvNet] · CPC title

• G06F7/505

  in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination · CPC title

• G06N3/063 Primary

  using electronic means · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title