Data compressor logic circuit

Patent metadata

Field	Value
Publication number	US-10756753-B2
Application number	US-201816170723-A
Country	US
Kind code	B2
Filing date	Oct 25, 2018
Priority date	Oct 25, 2018
Publication date	Aug 25, 2020
Grant date	Aug 25, 2020

Abstract

A compressor includes a logic circuit having transistors of a first channel type to receive a plurality of bit signals, and transistors of a second channel type, different from the first channel type, to receive the plurality of bit signals. The transistors of the first channel type are configured to generate an XOR logic output based on the plurality of bit signals, and the transistors of the second channel type are configured to generate, substantially simultaneous with the generation of the XOR logic output, an XNOR logic output based on the plurality of bit signals. The compressor includes NAND gates to receive multiplicand and multiplier bit signals.

First claim

What is claimed is:

1. A compressor, comprising:
first, second, and third logic gates each having respective first and second input terminals and an output terminal, wherein the first, second, and third logic gates are configured to output respective first, second, and third partial product bits at the respective output terminals;
a first circuit having first and second input terminals electrically coupled to the respective output terminals of the first and second logic gates, wherein the first circuit is configured to perform an XOR or XNOR logic operation on the first partial product bit or the second partial product bit to generate a resultant respective XOR or XNOR logic operation bit corresponding to one or more select signals; and
a first multiplexer having:
a first multiplexer select input terminal electrically coupled to the first circuit, and
a first multiplexer output terminal,
wherein the first multiplexer is configured to select a carry-out bit from among at least the first partial product bit and a third partial product bit based on the one or more select signals received at the first multiplexer select input terminal.

2. The compressor of claim 1 , wherein each of the first, second, and third logic gates is configured to perform a NAND logic operation on a respective multiplicand bit and a respective multiplier bit received at, the respective input terminals.

3. The compressor of claim 1 , wherein the output terminal of the third logic gate is electrically coupled to a data terminal of the first multiplexer and to a second circuit, and further comprising:
a fourth logic gate having an output terminal electrically coupled to the second circuit and to a second multiplexer,
wherein the second multiplexer is configured to select and output a carry signal at a second multiplexer output terminal.

4. The compressor of claim 1 , further comprising:
a first multiplexer having a first data input terminal electrically coupled to the first output terminal of the first logic gate.

5. The compressor of claim 4 , further comprising:
a fourth logic gate having a output terminal electrically coupled to a second circuit and to a second multiplexer, and
wherein the output terminal of the third logic gate is electrically coupled to a second data input terminal of the first multiplexer and to the second circuit, and wherein the second multiplexer is configured to select and output a carry signal at a second multiplexer output terminal.

6. A method, comprising:
receiving a first multiplicand bit and a first multiplier bit;
performing, with a first NAND circuit, a logic NAND operation on the first multiplicand bit and the first multiplier bit, to generate a first output bit;
receiving a second multiplicand bit and a second multiplier bit;
performing, with a second NAND circuit, a logic NAND operation on the second multiplicand bit and the second multiplier bit, to generate a second output bit;
performing a logic XOR operation with the first and second output bits to generate a first select signal;
receiving a third multiplicand bit and a third multiplier bit;
performing, with a third NAND circuit, a logic NAND operation on the third multiplicand bit and the third multiplier bit, to generate a third output bit; and
selecting, at the multiplexer, a carry-out bit from among the first output bit and the third output bit based on the state of the first select signal.

7. The method of claim 6 , further comprising:
performing, substantially simultaneously with the logic XOR operation, a logic XNOR operation with the first and second output bits to generate a second select signal, and
selecting, at the multiplexer, a carry-out bit from the first output bit and the third output bit based on the states of the first and second select signals.

8. A compressor, comprising:
a first circuit having pairs of first and second partial product bits coupled to corresponding first and second input terminals of the first circuit, wherein the first circuit is configured to perform an XOR or XNOR logic operation on the first partial product bit or the second partial product bit to generate a resultant respective XOR or XNOR logic operation bit corresponding to one or more first select signals; and
a second circuit having pairs of third and fourth partial product bits coupled to corresponding first and second input terminals of the second circuit, wherein the second circuit is configured to perform an XOR or XNOR logic operation on the third partial product bit or the fourth partial product bit to generate a resultant respective XOR or XNOR logic operation bit corresponding to one or more second select signals.

9. The compressor of claim 8 , wherein the first and third partial product bits are electrically coupled to first and second data terminals of a first multiplexer, wherein the first multiplexer is configured to select a carry-out bit from among at least the first partial product bit and a third partial product bit based on the one or more first select signals received at the first multiplexer.

10. The compressor of claim 8 , wherein the fourth partial product bit is electrically coupled to the second circuit and to a second multiplexer, and wherein the second multiplexer is configured to select and output a carry data signal at a second multiplexer output terminal.

11. A compressor, comprising:
a first circuit having one or more of first and second partial product bits input on first and second input terminals of the first circuit, wherein the first circuit is configured to perform an XOR or XNOR logic operation on the first partial product bit or the second partial product bit to generate a resultant respective XOR or XNOR logic operation bit corresponding to one or more first select signals; and
a second circuit having one or more of third and fourth partial product bits input on first and second input terminals of the second circuit, wherein the second circuit is configured to perform an XOR or XNOR logic operation on the third partial product bit or the fourth partial product bit to generate a resultant respective XOR or XNOR logic operation bit corresponding to one or more second select signals;
wherein the first, second, third, and fourth partial product bits correspond to respective outputs of first, second, third, and fourth logic gates, wherein each logic gate comprises respective first and second input terminals and an output terminal.

12. The compressor of claim 11 , wherein the first circuit comprises first and second input terminals electrically coupled to the output terminals of the first and second logic gates, and wherein the second circuit comprises first and second input terminals electrically coupled to the output terminals of the third and fourth logic gates.

Assignees

• Advanced Risc Mach Ltd

Inventors

• Shekhar Shardendu
• Chen Andy Wangkun
• Chong Yew Keong

Classifications

• H03K19/20 Primary

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title

• H03M7/005 Primary

  using semiconductor devices · CPC title

• H03K19/0944 Primary

  using MOSFET {or insulated gate field-effect transistors, i.e. IGFET}(H03K19/096 takes precedence) · CPC title

• H03M7/28

  Programmable structures, i.e. where the code converter contains apparatus which is operator-changeable to modify the conversion process · CPC title

• H03M7/6011

  Encoder aspects · CPC title