Memory device and computing device using the same

Patent metadata

Field	Value
Publication number	US-2020257500-A1
Application number	US-201916578507-A
Country	US
Kind code	A1
Filing date	Sep 23, 2019
Priority date	Feb 8, 2019
Publication date	Aug 13, 2020
Grant date	—

Abstract

A memory device is provided. The memory device includes: a memory cell configured to store weight data, a buffer memory configured to read the weight data from the memory cell, an input/output pad configured to receive input data and a multiply-accumulate (MAC) operator configured to receive the weight data from the buffer memory and receive the input data from the input/output pad to perform a convolution operation of the weight data and the input data, wherein the input data is provided to the MAC operator during a first period, and wherein the MAC operator performs the convolution operation of the weight data and the input data during a second period overlapping with the first period.

First claim

1 . A memory device comprising:
a memory cell configured to store weight data; a buffer memory configured to read the weight data from the memory cell; an input/output pad configured to receive input data; and a multiply-accumulate (MAC) operator configured to receive the weight data from the buffer memory and receive the input data from the input/output pad to perform a convolution operation of the weight data and the input data, wherein the input data is provided to the MAC operator during a first period, and wherein the MAC operator performs the convolution operation of the weight data and the input data during a second period overlapping with the first period.

2 . The memory device of claim 1 , wherein the weight data is provided to the MAC operator during a third period overlapping with the first period.

3 . The memory device of claim 1 , wherein before the input data is provided to the MAC operator, the buffer memory reads the weight data from the memory cell.

4 . The memory device of claim 1 , wherein the input data includes first and second input data,
wherein the weight data includes first and second weight data, wherein the first and second input data are provided to the MAC operator during first and second subperiods, respectively, wherein the first and second weight data are provided to the MAC operator during third and fourth sub-periods, respectively, and wherein the first stub-period overlaps with the third sub-period, and the second sub-period overlaps with the fourth sub-period.

5 . The memory device of claim 1 , wherein the weight data includes first and second weight bits,
wherein the input data includes first and second input bits, wherein the MAC operator includes a first multiplier and first to third accumulators, wherein performing the convolution operation by the MAC operator comprises performing a multiplication operation of the weight data and the input data by the first multiplier, and wherein performing the multiplication operation by the first multiplier comprises, by the first multiplier, calculating a first product of the first weight bit and the first input bit and providing the first product to the first accumulator, calculating a second product of the second weight bit and the first input bit and providing the second product to the second accumulator, calculating a third product of the first weight bit and the second input bit and providing the third product to the second accumulator, and calculating a fourth product of the second weight bit and the second input bit and providing the fourth product to the third accumulator.

6 . The memory device of claim 5 , wherein an output of the first accumulator is a least significant bit (LSB) of a product of the weight data and the input data.

7 . The memory device of claim 5 , wherein the second accumulator outputs a sum of the second product and the third product.

8 . The memory device of claim 1 , further comprising a result output buffer configured to store a convolution operation result of the weight data and the input data.

9 . The memory device of claim 8 , wherein the convolution operation result stored in the result output buffer is outputted through the input/output pad.

10 . The memory device of claim 1 , further comprising a result output pad which outputs a convolution operation result of the weight data and the input data and is different from the input/output pad.

11 . The memory device of claim 10 , wherein the MAC operator provides the convolution operation result to the result output pad during a fourth period overlapping with the second period.

12 . A memory device comprising:
a buffer memory configured to store weight data including first and second weight bits; an input/output pad configured to receive input data including first and second input bits; and a MAC operator including first to third accumulators and configured to receive the weight data and the input data and perform a convolution operation of the weight data and the input data, wherein performing the convolution operation of the weight data and the input data by the MAC operator comprises, calculating a first product of the first weight bit and the first input bit and providing the first product to the first accumulator, calculating a second product of the second weight bit and the first input bit and providing the second product to the second accumulator, calculating a third product of the first weight bit and the second input bit and providing the third product to the second accumulator, and calculating a fourth product of the second weight bit and the second input bit and providing the fourth product to the third accumulator.

13 . The memory device of claim 12 , wherein the first product and the second product are performed in parallel, and
wherein the third product and the fourth product are performed in parallel.

14 . The memory device of claim 12 , wherein performing the convolution operation by the MAC operator comprises performing a multiplication operation of the weight data and the input data by the MAC operator, and
wherein an output of the first accumulator is a least significant bit (LSB) of the multiplication operation.

15 . The memory device of claim 12 , wherein the input data is provided to the MAC operator during a first period, and
wherein the MAC operator performs the convolution operation during a second period overlapping with the first period.

16 . The memory device of claim 12 , herein the input data is provided to the MAC operator during a first period, and
wherein the weight data is provided to the MAC operator during a third period overlapping with the first period.

17 . The memory device of claim 12 , further comprising a memory cell configured to store the weight data,
wherein the weight data is read from the memory cell and stored in the buffer memory.

18 . The memory device of claim 17 , wherein before the MAC operator receives the input data, the weight data is read from the memory cell to the buffer memory.

19 - 20 . (canceled)

21 . A memory device comprising:
a memory cell configured to store weight data; a buffer memory configured to read the weight data from the memory cell; an input/output pad configured to receive input data; and a MAC operator configured to perform a convolution operation of the weight data and the input data, wherein the buffer memory reads the weight data from the memory cell before the input data is provided to the input/output pad, wherein the input data is provided to the MAC operator from the input/output pad during a first period, and wherein the weight data is provided to the MAC operator from the buffer memory during a second period overlapping with the first period.

22 - 26 . (canceled)

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Ga Ram

Classifications

• G06F3/0656

  Data buffering arrangements · CPC title

• G06F3/0611

  in relation to response time · CPC title

• G06N3/063 Primary

  using electronic means · CPC title

• G06F17/153

  Multidimensional correlation or convolution · CPC title

• G06F13/1673 Primary

  using buffers · CPC title