Flexible hardware accelerators for masking conversions with a power of two modulus
US-12499277-B2 · Dec 16, 2025 · US
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in bit-serial fashion, i.e. having a single digit-handling circuit treating all denominations after each other
in bit-serial fashion, i.e. having a single digit-handling circuit treating all denominations after each other · Cooperative Patent Classification (CPC)
Computing, optics, measurement, and control technologies.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | G06F7/504 |
| Official title | in bit-serial fashion, i.e. having a single digit-handling circuit treating all denominations after each other |
| Display label | in bit-serial fashion, i.e. having a single digit-handling circuit treating all denominations after each other |
| Total patents | 21 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is declining.
| Year | Patents |
|---|---|
| 2017 | 1 |
| 2018 | 3 |
| 2019 | 2 |
| 2020 | 3 |
| 2022 | 3 |
| 2023 | 3 |
| 2024 | 4 |
| 2025 | 2 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Processing apparatus and method of processing add operation therein
US-12423055-B2 · Sep 23, 2025 · US
Flexible hardware accelerators for masking conversions with a power of two modulus
US-2024338492-A1 · Oct 10, 2024 · US
Device and method with in-memory computing
US-2024231757-A9 · Jul 11, 2024 · US
Device and method with in-memory computing
US-2024134606-A1 · Apr 25, 2024 · US
Method and apparatus for operating memory processor
US-2024103809-A1 · Mar 28, 2024 · US
Multiple Input Serial Adder
US-2023367549-A1 · Nov 16, 2023 · US
Compute-in memory (cim) device and computing method thereof
US-2023333814-A1 · Oct 19, 2023 · US
Alternative data selector, full adder and ripple carry adder
US-11581894-B2 · Feb 14, 2023 · US
Protection of an iterative calculation
US-11456853-B2 · Sep 27, 2022 · US
Alternative data selector, full adder and ripple carry adder
US-2022271756-A1 · Aug 25, 2022 · US
Bit-serial linear algebra processor
US-11275713-B2 · Mar 15, 2022 · US
Protection of an iterative calculation
US-2020313846-A1 · Oct 1, 2020 · US
Processing apparatus and method of processing add operation therein
US-2020159495-A1 · May 21, 2020 · US
Connected devices information
US-10585674-B2 · Mar 10, 2020 · US
Bit-serial linear algebra processor
US-2019377707-A1 · Dec 12, 2019 · US
Connected devices information
US-2019056959-A1 · Feb 21, 2019 · US
Apparatus and method for estimating a shift amount when performing floating-point subtraction
US-10140093-B2 · Nov 27, 2018 · US
Apparatus and method for estimating a shift amount when performing floating-point subtraction
US-2018285076-A1 · Oct 4, 2018 · US
Transformation on input operands to reduce hardware overhead for implementing addition
US-10037190-B2 · Jul 31, 2018 · US