Apparatus and method for estimating a shift amount when performing floating-point subtraction

Patent metadata

Field	Value
Publication number	US-10140093-B2
Application number	US-201715473841-A
Country	US
Kind code	B2
Filing date	Mar 30, 2017
Priority date	Mar 30, 2017
Publication date	Nov 27, 2018
Grant date	Nov 27, 2018

Abstract

An apparatus and method are provided for estimating a shift amount when employing processing circuitry to perform a subtraction operation to subtract a second significand value of a second floating-point operand from a first significand value of a first floating-point operand in order to generate a difference value. Shift estimation circuitry then determines an estimated shift amount to be applied to the difference value. The shift estimation circuitry comprises significand analysis circuitry to generate, from analysis of the significand values of the two floating-point operands, a first bit string identifying a most significant bit position within the difference value that is predicted to have its bit set to a determined value. In parallel, shift limiting circuitry generates from an exponent value a second bit string identifying a shift limit bit position. The shift limiting circuitry has computation circuitry to perform, for each bit position in at least a subset of bit positions of the second bit string, an associated computation using bits of the exponent value to determine a value for that bit position within the second bit string. The associated computation is different for different bit positions. Combining circuitry then generates a combined bit string from the first and second bit strings, and shift determination circuitry determines the estimated shift amount from the combined bit string.

First claim

We claim:

1. An apparatus comprising:
processing circuitry to perform a subtraction operation to subtract a second significand value of a second floating-point operand from a first significand value of a first floating-point operand in order to generate a difference value; and
shift estimation circuitry to determine an estimated shift amount to be applied to the difference value, the shift estimation circuitry comprising:
significand analysis circuitry to generate, from analysis of the first and second significand values, a first bit string identifying a most significant bit position within the difference value that is predicted to have its bit set to a determined value;
shift limiting circuitry to generate from an exponent value a second bit string identifying a shift limit bit position, the shift limiting circuitry having computation circuitry to perform, for each bit position in at least a subset of bit positions of the second bit string, an associated computation using bits of the exponent value to determine a value for that bit position within the second bit string, the associated computation being different for different bit positions;
combining circuitry to generate a combined bit string from the first and second bit strings; and
shift determination circuitry to determine the estimated shift amount from the combined bit string.

2. An apparatus as claimed in claim 1 , wherein, prior to the subtraction operation being performed the first and second floating-point operands are arranged to have an exponent value that is the same, and that exponent value is the exponent value used by the shift limiting circuitry.

3. An apparatus as claimed in claim 1 , wherein said at least a subset of bit positions comprises a number of bit positions at least equal to the number of bit positions in the difference value.

4. An apparatus as claimed in claim 1 , wherein the associated computation for each bit position in said at least a subset of bit positions of the second bit string is at least logically equivalent to a computation that uses each bit of the exponent value at most once.

5. An apparatus as claimed in claim 4 , wherein the associated computation for each bit position in said at least a subset of bit positions of the second bit string performs a sequence of logical operations on the bits of the exponent value.

6. An apparatus as claimed in claim 5 , wherein the sequence of logical operations comprises one or more of AND, OR and NOT operations.

7. An apparatus as claimed in claim 1 , wherein the significand analysis circuitry and shift limiting circuitry are arranged to operate in parallel.

8. An apparatus as claimed in claim 7 , wherein the shift limiting circuitry has a logic depth no greater than the logic depth of the significand analysis circuitry.

9. An apparatus as claimed in claim 1 , wherein:
the significand analysis circuitry is arranged to generate the first bit string such that a bit position within the first bit string is set to a first value to identify said most significant bit position;
the shift limiting circuitry is arranged to generate the second bit string such that a bit position within the second bit string is set to the first value to identify the shift limit bit position; and
the shift determination circuitry is arranged to determine the estimated shift amount by detecting a number of leading bit positions within the combined bit string that are set to a second value different to said first value.

10. An apparatus as claimed in claim 9 , wherein the shift limiting circuitry is arranged to generate the second bit string such that at most one bit position within the second bit string is set to the first value.

11. An apparatus as claimed in claim 9 , wherein said combining circuitry is arranged to perform a logical OR operation on the first and second bit strings to generate the combined bit string.

12. An apparatus as claimed in claim 9 , wherein said first value is a logic 1 value and said second value is a logic 0 value.

13. An apparatus as claimed in claim 1 , wherein said determined value is a logic 1 value.

14. An apparatus as claimed in claim 1 , wherein:
said computation circuitry includes no limit detection circuitry to set a no limit flag when the exponent value is large enough to allow it to be adjusted by an amount sufficient to compensate for a maximum possible shift amount for the difference value; and
the computation circuitry is arranged, when the no limit flag is set, to generate a default bit sequence for the second bit string that identifies absence of the shift limit bit position.

15. An apparatus as claimed in claim 14 , wherein the no limit detection circuitry performs a logical OR operation on a number of most significant bits of the exponent value, the number of most significant bits being dependent on a number of bits used to specify the exponent value and the maximum possible shift amount.

16. An apparatus as claimed in claim 14 , wherein the default bit sequence is an all zeros bit sequence.

17. An apparatus as claimed in claim 1 , wherein:
the computation circuitry is arranged to set a most significant bit position in the second bit string to identify the shift limit bit position when the exponent value is one of a minimum exponent value for a normal floating-point value and a reserved exponent value used for a subnormal floating-point value, setting of the most significant bit position in the second bit string causing the shift determination circuitry to determine the estimated shift amount to indicate that no shift is to be applied to the difference value.

18. An apparatus as claimed in claim 17 , wherein the exponent value is expressed as a biased exponent value, and the computation circuitry is arranged to set a most significant bit position in the second bit string to identify the shift limit bit position when the biased exponent value is 1 or 0.

19. An apparatus as claimed in claim 1 , further comprising subnormal condition detection circuitry to determine when the estimated shift amount is constrained by the shift limit bit position, rather than the most significant bit position with the difference value that is predicted to have its bit set to a determined value, and on such detection to issue a signal to cause a result exponent to be set to a reserved exponent value used for a subnormal floating-point value.

Assignees

• Advanced Risc Mach Ltd

Inventors

• Lutz David Raymond
• Caulfield Ian Michael

Classifications

• G06F7/485 Primary

  Adding; Subtracting {(G06F7/4833, G06F7/4836 take precedence)} · CPC title

• G06F7/49921

  Saturation, i.e. clipping the result to a minimum or maximum value · CPC title

• G06F7/57

  Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations {(G06F7/49, G06F7/491 take precedence)} · CPC title

• G06F7/504 Primary

  in bit-serial fashion, i.e. having a single digit-handling circuit treating all denominations after each other · CPC title

• G06F5/012

  in floating-point computations · CPC title