Integration of a non-volatile memory (NVM) cell and a logic transistor and method therefor
US-9318568-B2 · Apr 19, 2016 · US
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Perera Asanga H patents
Perera Asanga H holds 5 patents in our database, with recent filings and technology areas summarized below.
| Metric | Value |
|---|---|
| Total patents | 5 |
| Recent patents | 0 |
| First publication | Jul 14, 2015 |
| Latest publication | Apr 19, 2016 |
Filing trend
Year-over-year patent counts for this assignee.
Recent patents
Latest publications where this party is an assignee.
Integrated split gate non-volatile memory cell and logic device
US-9252246-B2 · Feb 2, 2016 · US
Methods and structures for charge storage isolation in split-gate memory arrays
US-9136360-B1 · Sep 15, 2015 · US
Integration of a non-volatile memory (NVM) cell and a logic transistor and method therefor
US-9105748-B1 · Aug 11, 2015 · US
Integrated split gate non-volatile memory cell and logic structure
US-9082650-B2 · Jul 14, 2015 · US
Notable patents
Representative or frequently cited publications from precomputed assignee stats.
Integration of a non-volatile memory (NVM) cell and a logic transistor and method therefor
US-9318568-B2 · Apr 19, 2016 · US
Integrated split gate non-volatile memory cell and logic device
US-9252246-B2 · Feb 2, 2016 · US
Methods and structures for charge storage isolation in split-gate memory arrays
US-9136360-B1 · Sep 15, 2015 · US
Integration of a non-volatile memory (NVM) cell and a logic transistor and method therefor
US-9105748-B1 · Aug 11, 2015 · US
Integrated split gate non-volatile memory cell and logic structure
US-9082650-B2 · Jul 14, 2015 · US
Top CPC classifications
Most common classification codes in this portfolio.
| CPC | Patents |
|---|---|
| H10D64/017 | 3 |
| H10B41/43 | 3 |
| H10D30/0411 | 3 |
| H10D30/6892 | 2 |
| H10D64/035 | 2 |
Technology areas
Mapped technology topics for this assignee.
| Technology | Patents |
|---|---|
| Electricity | 5 |