Integrated split gate non-volatile memory cell and logic device

Patent metadata

Field	Value
Publication number	US-9252246-B2
Application number	US-201313972372-A
Country	US
Kind code	B2
Filing date	Aug 21, 2013
Priority date	Aug 21, 2013
Publication date	Feb 2, 2016
Grant date	Feb 2, 2016

Abstract

A method of making a semiconductor structure includes forming a select gate and a charge storage layer in an NVM region. A control gate is formed by depositing a conformal layer followed by an etch back. A patterned etch results in leaving a portion of the charge storage layer over the select gate and under the control gate and to remove the charge storage layer from the logic region. A logic gate structure formed in a logic region has a metal work function surrounded by an insulating layer.

First claim

What is claimed is:

1. A method of making a semiconductor structure using a substrate having a non-volatile memory (NVM) region and a logic region, comprising:
forming a select gate over the substrate in the NVM region;
forming a charge storage layer over the substrate including over the logic region and the NVM region, wherein over the NVM region includes over the select gate;
forming a conformal conductive layer over the charge storage layer including over the logic region and the NVM region, wherein over the NVM region includes over the select gate;
etching the conformal conductive layer to form a control gate adjacent to a sidewall of the select gate;
forming a mask over a portion of the charge storage layer, the control gate, and a portion of the select gate; and
performing a patterned etch of the charge storage layer using the mask to leave the portion of the charge storage layer over the select gate and under the control gate and to remove the charge storage layer from the logic region;
forming a gate structure in the logic region having a work function metal surrounded by an insulating layer.

2. The method of claim 1 , further comprising:
forming a hard mask over the NVM region after performing the patterned etch of the charge storage layer and prior to forming the gate structure in the logic region;
wherein the forming the gate structure comprises:
forming a high k dielectric over the logic region; and
forming the work function metal over the high k dielectric.

3. The method of claim 2 , wherein the forming the gate structure further comprises forming a polysilicon layer over the work function metal; and
patterning the polysilicon layer, the work function metal, and the high k dielectric.

4. The method of claim 2 , wherein the forming the hard mask comprises forming a nitride layer.

5. The method of claim 4 , wherein the forming the hard mask further comprises forming a first oxide layer prior to forming the nitride layer and forming a second oxide layer over the nitride layer.

6. The method of claim 3 , wherein forming the insulating layer comprises:
forming a first nitride layer after the patterning the polysilicon layer, the work function metal, and the high k dielectric;
forming a first oxide layer on the first nitride layer; and
etching the first nitride layer and the first oxide layer using an anisotropic etch to form a first implant mask for the gate structure.

7. The method of claim 6 , further comprising performing an extension implant using the first implant mask.

8. The method of claim 7 , wherein the forming the insulating layer further comprises:
forming a second oxide layer over the logic region including over the first implant mask;
forming a second nitride layer over the second oxide layer;
wherein the method further comprises etching the second nitride layer and the second oxide layer to form a second implant mask; and
performing a deep source/drain implant using the second implant mask for the gate structure.

9. The method of claim 8 , further comprising removing a portion of the hard mask prior, the first oxide layer, and the first nitride layer from the NVM region prior to forming the second nitride layer which leaves a first layer in the NVM region, wherein:
the second nitride layer is formed on the first layer in the NVM region;
the second oxide layer is formed on the second nitride layer in the NVM region;
the etching the second nitride layer and the second oxide layer etches the first layer to form an NVM implant mask; and
the deep source/drain implant uses the NVM implant mask for the select gate and the control gate.

10. The method of claim 1 , wherein the step of forming the charge storage layer comprises forming a layer comprising nanocrystals surrounded by an insulating material.

11. The method of claim 1 , further comprising forming a first layer of thermal oxide on the substrate in the NVM region, wherein the forming the select gate is further characterized as being formed on the first layer of thermal oxide.

12. The method of claim 11 , further comprising:
removing a portion of the first layer of thermal oxide adjacent to the select gate; and
forming a second layer of thermal oxide adjacent to the select gate prior to forming the conformal conductive layer,
wherein the charge storage layer is formed on the second layer of thermal oxide.

13. The method of claim 12 , further comprising etching the substrate adjacent to the select gate prior to forming the second layer of thermal oxide.

14. A method of making a semiconductor structure using a substrate having a non-volatile memory (NVM) region and a logic region, comprising:
forming a select gate in the NVM region;
forming a charge storage layer over the substrate in the NVM region;
forming a control gate adjacent to a first side of the select gate;
forming a first hard mask over the NVM region;
forming a high k dielectric over the logic region after forming the first hard mask;
forming a work function metal over the high k dielectric;
forming a conductive layer over the work function metal; and
patterning the conductive layer, the work function metal, and the high k dielectric to form a gate stack.

15. The method of claim 14 , further comprising:
forming a second hard mask over the NVM region and the logic region;
removing the second hard mask and a portion of the first hard mask from the NVM region;
performing an etch to result in a first sidewall spacer around the gate stack and a second sidewall spacer around the select gate and control gate; and
performing an implant using the first sidewall spacer and the second sidewall spacer as masks.

16. The method of claim 14 , further comprising patterning the charge storage layer to remove a first portion of the charge storage layer from over the select gate and leave a second portion over the select gate.

17. The method of claim 16 , wherein the forming the charge storage layer is further characterized as forming a nanocrystal layer.

18. The method of claim 17 , further comprising:
performing a first thermal oxidation on the substrate prior to forming the select gate;
removing oxide from the substrate prior after forming the select gate; and
performing a second thermal oxidation prior to forming the control gate;
wherein the control gate is formed on oxide formed by the second thermal oxidation.

19. The method of claim 18 wherein the forming the first hard mask layer comprises:
forming a first oxide layer;
forming a nitride layer over the first oxide layer; and
forming a second oxide layer over the nitride layer.

Assignees

• Perera Asanga H
• Hong Cheong Min
• Kang Sung-Taeg
• Yater Jane A
• Freescale Semiconductor Inc

Inventors

• Perera Asanga H
• Hong Cheong Min
• Kang Sung-Taeg
• Yater Jane A

Classifications

• H10D64/035

  comprising conductor-insulator-conductor-insulator-semiconductor structures · CPC title

• H10D30/6893

  wherein the floating gate has multiple non-connected parts, e.g. multi-particle floating gate · CPC title

• H10D30/0411 Primary

  of FETs having floating gates · CPC title

• H01L21/28273

  Electricity · mapped topic

• H01L29/42332

  Electricity · mapped topic