Graded well implantation for asymmetric transistors having reduced gate electrode pitches

Patent metadata

Field	Value
Publication number	US-9449826-B2
Application number	US-69288610-A
Country	US
Kind code	B2
Filing date	Jan 25, 2010
Priority date	Jan 30, 2009
Publication date	Sep 20, 2016
Grant date	Sep 20, 2016

Abstract

In sophisticated semiconductor devices, an asymmetric transistor configuration may be obtained on the basis of an asymmetric well implantation while avoiding a tilted implantation process. For this purpose, a graded implantation mask may be formed, such as a graded resist mask, which may have a higher ion blocking capability at the drain side compared to the source side of the asymmetric transistor. For instance, the asymmetric configuration may be obtained on the basis of a non-tilted implantation process with a high degree of performance gain and may be accomplished irrespective of the technology standard under consideration.

First claim

What is claimed:

1. A method, comprising:
forming an implantation mask above a semiconductor region, said implantation mask having a first ion blocking capability above a first transistor internal area of a transistor and having a second ion blocking capability above a second transistor internal area of said transistor, said first and second ion blocking capabilities differing from each other, wherein the first transistor internal area is used for forming a source region and wherein the second transistor internal area is used for forming a drain region;
implanting a well dopant species into said first and second transistor internal areas on the basis of said implantation mask; and
forming a gate electrode above a channel area of said semiconductor region, said channel area laterally separating said first and second transistor internal areas.

2. The method of claim 1 , wherein forming said implantation mask comprises forming an ion blocking material with a varying thickness above said first and second transistor internal areas.

3. The method of claim 2 , wherein said ion blocking material comprises a resist material.

4. The method of claim 2 , wherein said ion blocking material comprises a non-resist material.

5. The method of claim 4 , wherein forming said ion blocking material comprises depositing said non-resist material, locally varying an etch behavior of said non-resist material and removing material of said non-resist material on the basis of said locally varying etch behavior.

6. A method comprising:
forming an implantation mask above a semiconductor region, said implantation mask having a first ion blocking capability above a first transistor internal area of a transistor and having a second ion blocking capability above a second transistor internal are of said transistor, said first and second ion blocking capabilities differing from each other, wherein forming said implantation mask comprises forming an ion blocking material with a varying thickness above said first and second transistor internal areas, wherein said ion blocking material comprises a non-resist material, wherein forming said ion blocking material comprises depositing said non-resist material, locally varying an etch behavior of said non-resist material and removing material of said non-resist material on the basis of said locally varying etch behavior, and wherein locally varying said etch behavior comprises forming a resist mask above said non-resist material and performing an implantation process using a tilt angle so as to introduce an implantation species locally varying said etch behavior;
implanting a well dopant species into said first and second transistor internal areas on the basis of said implantation mask; and
forming a gate electrode above a channel area of said semiconductor region, said channel area laterally separating said first and second transistor internal areas.

7. The method of claim 1 , further comprising forming an isolation structure prior to forming said implantation mask, wherein said isolation structure laterally delineates said semiconductor region.

8. The method of claim 1 , further comprising forming an isolation structure after forming said implantation mask, wherein said isolation structure laterally delineates said semiconductor region.

9. The method of claim 1 , wherein said first ion blocking capability is less than said second ion blocking capability.

10. The method of claim 1 , wherein said implantation mask covers a first transistor internal area and a second transistor internal area of a second transistor and wherein an ion blocking capability of said implantation mask above said first transistor internal area of said second transistor is substantially equal to an ion blocking capability of said implantation mask above said second transistor internal area of said second transistor, wherein the first transistor internal area of the second transistor is used for forming a source region and wherein the second transistor internal area of the second transistor is used for forming a drain region.

11. The method of claim 10 , wherein said first and second transistor internal areas of said transistors and said first and second transistor internal areas of said second transistor are formed in said semiconductor region without providing an intermediate isolation structure between said transistor and said second transistor.

12. The method of claim 1 , further comprising implanting an additional portion said well dopant species into said first and second transistor internal areas without using said implantation mask.

13. The method of claim 1 , wherein said gate electrode is formed to have a length of approximately 50 nm or less.

14. The method of claim 1 , wherein implanting the well dopant species into said first and second transistor internal areas on the basis of said implantation mask comprises implanting the well dopant species into said first and second transistor internal areas so that the overall amount of dopant species decreases from the first transistor internal area to the second transistor internal area.

15. A method, comprising:
forming a graded implantation mask above a first transistor internal area and a second transistor internal area of a transistor, said graded implantation mask providing a first ion blocking capability for said first transistor internal area and a second increased ion blocking capability for said second transistor internal area, wherein said second ion blocking capability is greater than said first ion blocking capability, wherein the first transistor internal area is used for forming a source region and wherein the second transistor internal area is used for forming a drain region;
forming a gate electrode after forming said graded implantation mask;
introducing a well dopant species in said first and second transistor internal areas on the basis of said implantation mask; and
forming a drain and source regions on the basis of said first and second transistor internal areas so as to obtain an asymmetric transistor configuration.

Assignees

• Mulfinger G Robert
• Wei Andy
• Hoentschel Jan
• Papageorgiou Vassilios
• Advanced Micro Devices Inc

Inventors

• Mulfinger G Robert
• Wei Andy
• Hoentschel Jan
• Papageorgiou Vassilios

Classifications

• H10P30/222

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H10P30/212

  Through-implantation · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/22 Primary

  using masks · CPC title

• H10D30/601

  having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  (lightly doped source or drain extensions for TFTs H10D30/6715) · CPC title