Semiconductor package having spacer layer

Patent metadata

Field	Value
Publication number	US-RE50796-E
Application number	US-202217730974-A
Country	US
Kind code	E1
Filing date	Apr 27, 2022
Priority date	Oct 31, 2011
Publication date	Feb 10, 2026
Grant date	Feb 10, 2026

Abstract

Package assemblies for and methods of packaging integrated circuit chips are described. Disclosed package assemblies have spacers and recessed regions comprising IC chips. Architectural structures are provided that enable, for example, three dimensional (3D) packaging (or system in package (SiP) or multi-chip modules), systems-on-chip 3D packaging, and hybrid 3D bonding. Embodiments of the invention can be used, for example, to create logic-to-memory, memory-to-memory, and logic-to-logic interface stacking assemblies.

First claim

We claim:

1 . A device comprising:
a packaging substrate having a surface wherein the surface has a recess formed therein; a first integrated circuit die disposed in the recess of the packaging substrate wherein the first integrated circuit die has a surface; a raised patterned layer disposed on the surface of the packaging substrate, the raised patterned layer comprising a dielectric material; and a second integrated circuit die disposed directly on the raised patterned layer creating a cavity that is bordered defined at least partially by an inner surface of the raised patterned layer, the surface of the packaging substrate, and a surface of the second integrated circuit diethat faces the surface of the first integrated circuit die.

2 . The device of claim 1 wherein the first integrated circuit die also comprises a spacer layer disposed on the surface of the first integrated circuit die.

3 . The device of claim 1 wherein the packaging substrate is a careless coreless packaging substrate.

4 . The device of claim 1 wherein the packaging substrate is comprised of built-up layers of dielectric and conducting materials.

5 . The device of claim 1 wherein the cavity is a region having an airtight seal.

6 . The device of claim 1 wherein the first integrated circuit die is fully embedded in the packaging substrate.

7 . The device of claim 1 wherein the cavity comprises sensors or actuators that are electrically coupled to the package substrate.

8 . The device of claim 7 wherein the sensors or actuators are selected from the group consisting of mems RF switches, cantilever-based sensors, accelerometers, gyroscopes, oscillators, pizeoresistive piezoresistive sensors, passives, RFID systems, antennas, and or GPS systems.

9 . The device of claim 1 , further comprising an interconnect region directly electrically connecting the first integrated circuit die and the second integrated circuit die.

10 . A device comprising:
a mainboard assembly having a first side, wherein the mainboard assembly has a package assembly disposed on the first side and the package assembly comprises:
a packaging substrate having a surface wherein the surface has a recess formed therein;
a first integrated circuit die disposed in the recess of the packaging substrate wherein the first integrated circuit die has a surface;
a raised patterned layer disposed on the surface of the packaging, the raised patterned layer comprising a dielectric material; and
a second integrated circuit die disposed directly on the raised patterned layer creating a cavity that is bordered by an inner surface of the raised patterned layer and a surface of the second integrated circuit die that faces the surface of the first integrated circuit die.

11 . The device of claim 10 wherein the packaging substrate is a careless coreless packaging substrate.

12 . The device of claim 10 wherein the mainboard assembly has a second side, wherein the mainboard assembly has one or more additional devices disposed on the first or second side, and wherein the one or more additional devices are selected from the group consisting of processing devices, memory devices, signal processing devices, wireless communication devices, graphics controllers, input/output controllers, audio processors, power delivery components, and power management components.

13 . The device of claim 10 , further comprising an interconnect region directly electrically connecting the first integrated circuit die and the second integrated circuit die.

14 . A device comprising:
a packaging substrate having a surface wherein the surface has a recess formed therein; a first integrated circuit die disposed in the recess of the packaging substrate wherein the first integrated circuit die has a surface; a raised spacer layer disposed on the surface of the first integrated circuit die, the raised spacer layer having a bottom surface below the surface of the packaging substrate, and the raised spacer layer having a top surface above the surface of the packaging substrate, the raised spacer layer comprising a dielectric material; and a second integrated circuit die having a surface, the surface of the second integrated circuit die disposed directly on the raised spacer layer creating a cavity that is bordered by an inner surface of the raised spacer layer and the surface of the second integrated circuit die.

15 . The device of claim 14 , further comprising an interconnect region directly electrically connecting the first integrated circuit die and the second integrated circuit die.

16 . The device of claim 14 wherein the packaging substrate is a careless coreless packaging substrate.

17 . The device of claim 14 wherein the packaging substrate is comprised of built-up layers of dielectric and conducting materials.

18 . The device of claim 14 wherein the cavity is a region having an airtight seal.

19 . The device of claim 14 wherein the first integrated circuit die is fully embedded in the packaging substrate.

20 . The device of claim 14 wherein the cavity comprises sensors or actuators that are electrically coupled to the package substrate.

21 . A device comprising:
a packaging substrate having a surface wherein the surface has a recess formed therein; a first integrated circuit die disposed in the recess of the packaging substrate wherein the first integrated circuit die has a surface; a raised spacer layer disposed on the surface of the first integrated circuit die, the raised spacer layer having a bottom surface below the surface of the packaging substrate, and the raised spacer layer having a top surface above the surface of the packaging substrate; and a second integrated circuit die having a surface, the surface of the second integrated circuit die disposed directly on the raised spacer layer creating a cavity that is bordered by an inner surface of the raised spacer layer and the surface of the second integrated circuit die, wherein the cavity comprises sensors or actuators that are electrically coupled to the package substrate.

Assignees

• Exo Imaging Inc

Inventors

• Teh Weng Hong
• Guzek John S
• Zhong Shan

Classifications

• H10W72/851

  Dispositions of multiple connectors or interconnections · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/248 Primary

  Top-view layouts, e.g. mirror arrays · CPC title

• H10W90/722

  between stacked chips · CPC title