Multi-layer ceramic capacitor and method of manufacturing the same

USRE48877E · US · E1

Patent metadata
FieldValue
Publication numberUS-RE48877-E
Application numberUS-201216438225-A
CountryUS
Kind codeE1
Filing dateNov 13, 2012
Priority dateMar 30, 2012
Publication dateJan 4, 2022
Grant dateJan 4, 2022

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  1. Title

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Abstract

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A multi-layer ceramic capacitor has a structure where the dispersion, nd, of average grain size of the dielectric grains constituting the dielectric layer (a value (D90/D10) obtained by dividing D90 which is a grain size including 90% cumulative abundance of grains by D10 which is a grain size including 10% cumulative abundance of grains) is smaller than 4.

First claim

Opening claim text (preview).

The invention claimed is: 1. A multi-layer ceramic capacitor constituted by sintered dielectric layers and internal electrode layers alternately layered with one another, wherein dielectric grains constitute a sintered grain body which forms the sintered dielectric layers, and a dispersion, nd, of average grain size of the dielectric grains (a value (D90/D10) obtained by dividing D90 which is a grain size including 90% cumulative abundance of grains by D10 which is a grain size including 10% cumulative abundance of grains) is smaller than 4, said dielectric grains being sintered and grown to wherein an average size of sintered grains in the sintered grain body is greater than 300 nm but smaller than 1000 nm. 2. A multi-layer ceramic capacitor according to claim 1 , wherein the dielectric layer does not contain Mg. 3. A multi-layer ceramic capacitor according to claim 2 , wherein an average of the dielectric grains is greater than 300 nm but smaller than 100 nm. 4. A multi-layer ceramic capacitor according to claim 1 , wherein the dielectric layer contains 0.03 mol or less of Mg per 100 mol of BaTiO 3 . 5. A multi-layer ceramic capacitor according to claim 4 , wherein the dielectric layer contains 0.01 mol or more but 0.03 mol or less of Mg per 100 mol of BaTiO 3 . 6. A multi-layer ceramic capacitor according to claim 5 , wherein an average size of the dielectric grains is greater than 300 nm but smaller than 1000 nm. 7. A multi-layer ceramic capacitor according to claim 4 , wherein an average size of the dielectric grains is greater than 300 nm but smaller than 1000 nm. 8. A multi-layer ceramic capacitor according to claim 1 , wherein the multi-layer ceramic capacitor has an accelerated life of 25 hours or longer as measured by an accelerated life test conducted under conditions of 150° C. and 8.5 V/μm. 9. A multi-layer ceramic capacitor according to claim 1 , wherein the multi-layer ceramic capacitor has a specific dielectric constant of 5000 or greater. 10. A method of manufacturing a multi-layer ceramic capacitor comprising: a step to prepare a dielectric material powder whose average grain size is 200 nm or less, and a step to sinter the dielectric material powder in such a way that a dispersion of average grain size nd (grain size D90 equivalent to 90% cumulative abundance divided by grain size D10 equivalent to 10% cumulative abundance (D90/D10)) of dielectric grains constituting a dielectric layer becomes smaller than 4, and an average size of the dielectric grains becomes greater than 300 nm but smaller than 1000 nm. 11. A method of manufacturing multi-layer ceramic capacitor according to claim 10 , wherein an average grain size of the dielectric material powder is 80 nm or greater but 200 nm or smaller.

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Classifications

  • Products characterised by the absence or the low content of specific components, e.g. alkali metal free alumina ceramics · CPC title

  • Manganese oxides, manganates, rhenium oxides or oxide-forming salts thereof, e.g. MnO · CPC title

  • Vanadium oxides, vanadates or oxide forming salts thereof, e.g. magnesium vanadate · CPC title

  • Alkaline earth titanates · CPC title

  • Rare earth oxide or oxide forming salts thereof, e.g. scandium oxide · CPC title

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What does patent USRE48877E cover?
A multi-layer ceramic capacitor has a structure where the dispersion, nd, of average grain size of the dielectric grains constituting the dielectric layer (a value (D90/D10) obtained by dividing D90 which is a grain size including 90% cumulative abundance of grains by D10 which is a grain size including 10% cumulative abundance of grains) is smaller than 4.
Who is the assignee on this patent?
Taiyo Yuden Kk
What technology area does this patent fall under?
Primary CPC classification H01G4/1227. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 04 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (E1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).