Methods of forming semiconductor devices
US-2024387699-A1 · Nov 21, 2024 · US
USRE46464E · US · E1
| Field | Value |
|---|---|
| Publication number | US-RE46464-E |
| Application number | US-201514846479-A |
| Country | US |
| Kind code | E1 |
| Filing date | Sep 4, 2015 |
| Priority date | Dec 14, 2010 |
| Publication date | Jul 4, 2017 |
| Grant date | Jul 4, 2017 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
A method for forming a stair-step structure in a substrate is provided. An organic mask is formed over the substrate. A hardmask with a top layer and sidewall layer is formed over the organic mask. The sidewall layer of the hard mask is removed while leaving the top layer of the hardmask. The organic mask is trimmed. The hardmask is removed. The substrate is etched. The forming the hardmask, removing the sidewall layer, trimming the organic mask, and etching the substrate are repeated a plurality of times.
Opening claim text (preview).
What is claimed is: 1. A method for forming a stair-step structure in a substrate, comprising: a) forming an organic mask over the substrate; b) forming a hardmask with a top layer and sidewall layer over the organic mask; c) removing the sidewall layer of the hard mask while leaving the top layer of the hardmask; d) trimming the organic mask; e) removing the hardmask; f) etching the substrate through the organic mask; and g) repeating steps ab-f a plurality of times to form the stair-step structure. 2. The method, as recited in claim 1 , wherein a thickness of the top layer of the hardmask is greater than a thickness of the sidewall layer of the hardmask. 3. The method, as recited in claim 2 , wherein the trimming the organic mask forms a roof, formed from the top layer of the hardmask, where the organic mask has been trimmed away under the roof. 4. The method, as recited in claim 3 , wherein the thickness of the top layer is at least twice the thickness of the sidewall layer. 5. The method, as recited in claim 4 , wherein the forming the hardmask over the organic mask provides, comprises providing a bias. 6. The method, as recited in claim 5 , wherein the repeating steps ab-f is repeated at least 3 times. 7. The method, as recited in claim 6 , wherein steps ab-f are performed in a single plasma processing chamber. 8. The method, as recited in claim 7 , wherein the substrate comprises a plurality of layers, wherein each layer comprises at least two sublayers, wherein at least one of the at least two sublayers is a silicon layer. 9. The method, as recited in claim 1 , wherein the trimming the organic mask forms a roof, formed from the top layer of the hardmask, where the organic mask has been trimmed away under the roof. 10. The method, as recited in claim 1 , further comprising providing a descum after removing the hardmask to remove an organic mask foot before etching the substrate. 11. The method, as recited in claim 1 , wherein the forming the hardmask over the organic mask provides, comprises providing a bias. 12. The method, as recited in claim 1 , wherein the repeating steps ab-f is repeated at least 3 times. 13. The method, as recited in claim 1 , wherein steps ab-f are performed in a single plasma processing chamber. 14. A method for making a three dimensional memory structure, comprising: a) providing memory stack comprising a plurality of layers, wherein each layer comprises at least two sublayers; b) forming an organic mask over the memory stack; c) forming a hardmask with a top layer and sidewall layer over the organic mask; d) removing the sidewall layer of the hard mask while leaving the top layer of the hardmask; e) trimming the organic mask; f) removing the hardmask; g) etching the memory stack through the organic mask, so that portions of the memory stack not covered by the organic mask are etched a depth of the thickness of a layer of the plurality of layers; and h) repeating steps bc-g a plurality of times. 15. The method, as recited in claim 14 , further comprising providing a descum after removing the hardmask to remove an organic mask foot before etching the substrate. 16. The method, as recited in claim 14 , wherein the trimming the organic mask forms a roof, formed from the top layer of the hardmask, where the organic mask has been trimmed away under the roof. 17. The method, as recited in claim 14 , wherein steps bc-g are performed in a single plasma processing chamber.
by chemical means · CPC title
the material being a silicon oxide, e.g. SiO2 · CPC title
in the presence of a plasma [PECVD] · CPC title
for drying etching · CPC title
characterised by their composition, e.g. multilayer masks or materials · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.