SIMD operation method and SIMD appartus that implement SIMD operations without a large increase in the number of instructions

Patent metadata

Field	Value
Publication number	US-RE46277-E
Application number	US-49116309-A
Country	US
Kind code	E1
Filing date	Jun 24, 2009
Priority date	Nov 28, 2001
Publication date	Jan 17, 2017
Grant date	Jan 17, 2017

Abstract

An operation method has processing for applying a same type of operation in parallel to N M-bit operands to obtain N M-bit operation results executed on a computer. Here, N is an integer equal to or greater than 2 and M is an integer equal to or greater than 1. The operation method includes: an operation step of applying the type of operation to an N*M-bit provisional operand that is formed by concatenating the N M-bit operands, to obtain one N*M-bit provisional operation result, and generating correction information based on an effect had, by applying the operation, on each M bits of the provisional operation result from a bit that neighbors the M bits; and a correction step of correcting the provisional operation result in M-bit units with use of the correction information, to obtain the N M-bit operation results.

First claim

What is claimed is:

1. An operation method for having an operation apparatus execute (a) an existing operation that applies a predetermined type of operation to one N*M-bit first-bit-length operand, to obtain one N*M-bit first-bit length operation result, and (b) an SIMD (Single Instruction Multiple Data) operation used for applying N parallel operations that applies the predetermined type of operation in parallel to N M-bit second-bit-length operands to obtain N M-bit second-bit-length operation results, N being an integer equal to or greater than 2 and M being an integer equal to or greater than 1,
the operation apparatus implementing:
an operation instruction for instructing application of the predetermined type of operation on one of (c) the first-bit-length operand, and (d) the plurality of second-bit-length operands concatenated and considered to be a first-bit-length operand; and
an SIMD correction instruction for instructing correction of an operation result of the operation instruction to an operation result of the SIMD operation,
the operation apparatus comprising:
a storage unit storing the first-bit-length operation result, and correction information that is used in the correction:
the operation method comprising:
a decoding step of decoding the operation instruction and the SIMD correction instruction used for applying N parallel operations; and
an execution step of,
(e) when the operation instruction is decoded, applying the predetermined type of operation to one of (i) the first-bit-length operand, and (ii) the N second-bit length operands concatenated and considered to be a first-bit-length operand, to obtain one first-bit-length operation result, storing the obtained first-bit-length operation result in the storage unit, and generating correction information based on an effect had, by applying the predetermined type of operation, on each M bits of the first-bit-length operation result from a bit that neighbors the M bits, and storing the generated correction information in the storage unit, and
(f) when the SIMD correction instruction used for applying N parallel operations is decoded, correcting the stored first-bit-length operation result in M-bit units using the stored correction information, to obtain the N second-bit-length operation results,
wherein when executing the existing instruction, the operation instruction is decoded and an obtained first-bit-length operation result is considered to be an operation result of the existing operation, and
when executing the SIMD operation, the operation instruction is decoded, an obtained first-bit-length operation result is considered to be a provisional operation result, the SIMD operation is then decoded, and N second-bit-length operation results obtained by correcting the provisional operation result are considered to be an operation result of the SIMD operation.

2. The operation method of claim 1 ,
wherein in the execution step, when the SIMD correction instruction used for applying N parallel operations is decoded, M least; significant bits of the first-bit-length operation result are excluded from being corrected.

3. The operation method of claim 1 , wherein the execution apparatus further executes the SIMD operation used for applying N/P parallel operations that applies the same predetermined type of operation in parallel to N/P M*P-bit third-bit-length operands to obtain N/P M*P-bit third-bit-length operation results, P being an integer equal to or greater than 2 and equal to or less than N/2,
the decoding step further decodes the SIMD correction instruction used for applying N/P parallel operations, and
the execution step,
(a) when the operation instruction is decoded, applies the predetermined type of operation to the first-bit-length operand, the first-bit-length operand being one of (i) the N second-bit-length operands concatenated and considered to be a first-bit-length operand, and (ii) the N/P third-bit-length operands concatenated and considered to be a first-bit-length operand, to obtain a first-bit-length operation result, stores the obtained first-bit-length operation result in the storage unit, generates the correction information based on an effect had, by applying the predetermined type of operation, on each M bits of the first bit-length operation result from a bit that neighbors the M bits, and stores the generated correction information in the storage unit, and
(b) when the SIMD operation used for applying N/P parallel operations is decoded, corrects the stored first-bit-length operation result in M*P-bit units, using only parts of the stored correction information that correspond to an effect on each M*P-bit unit.

4. The operation method of claim 3 ,
wherein respective values of N, M and P are one of (a) N=8, M=8 and P=one of (i) 2, (ii) 4, and (iii) 2 and 4, and (b) N=4, M=16 and P=2.

5. The operation method of claim 1 ,
wherein the predetermined type of operation is any one of a plurality of types of operations,
the execution step, when a least significant bit is considered to be a first bit,
(a) when the operation instruction is decoded, generates the correction information, in M-bit units, based on the predetermined type of operation and a carry from an M*L-th bit to an M*L1-th bit according to the predetermined type of operation, the M*L+1-th bit having a value of one of(a) 0 or 1 and (b) 0 or −1, L being N integers from 0 to N−1, and
(b) when the SIMD correction instruction is decoded, performs, regardless of the predetermined type of the operation, one of (a) adding the stored correction information to the first-bit-length operation result in M-bit units, and (b) subtracting the correction information from the first-bit-length operation result in M-bit units, to obtain the NM-bit operation results.

6. The operation method of claim 5 ,
wherein the plurality of types of operations includes at least one of increment, decrement, dyadic add, and dyadic subtract,
the execution step, (a) when the operation instruction is decoded and the predetermined type is increment, increments the first-bit-length operand, to obtain a first-bit-length operation result, and generates the correction information, each M*L+1-th bit without a carry according to the operation being represented by a value −1 in the correction information, and each M*L+1-th bit with a carry according to the operation being represented by a value 0 in the correction information,
(b) when the operation instruction is decoded and the predetermined type is decrement, decrements the first-bit-length operand, to obtain a first-bit-length operation result, and generates the correction information, each M*L+1-th bit without a carry according to the operation being represented by a value 0 in the correction information, and each M*L+1-th bit with a carry according to the operation being represented by a value 1 in the correction information,
(c) when the operation instruction is decoded and the predetermined type is dyadic add, adds a first first-bit-length operand and a second first-bit-length operand to obtain first-bit-length operation result, the first first-bit-length operand being formed by concatenating N second-bit-length operands, and the second first-bit-length operand being formed by concatenating N second-bit-length operands, and generates the correction information, each M*L+1-th bit without a carry according to the operation being represented by a value 0 in the correction information, and each M*L+1-th bit with a carry according to the operation being represented by a value 1 in the correction information,
(d) when the operation instruction is decoded and the predetermined type is dyadic subtract, subtracts a second first-bit-length operand from a first first-bit-length operand to obtain a first-bit-length operation re

Assignees

• Suzuki Masato
• Socionext Inc

Inventors

• Suzuki Masato

Classifications

• G06F7/48 Primary

  using non-contact-making devices, e.g. tube, solid state device; using unspecified devices · CPC title

• G06F2207/3828

  Multigauge devices, i.e. capable of handling packed numbers without unpacking them · CPC title