Low-noise high efficiency bias generation circuits and method

US9778669B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9778669-B2
Application numberUS-201615059206-A
CountryUS
Kind codeB2
Filing dateMar 2, 2016
Priority dateJul 18, 2008
Publication dateOct 3, 2017
Grant dateOct 3, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Embodiments of signal bias generators and regulators are described generally herein. Other embodiments may be described and claimed.

First claim

Opening claim text (preview).

What is claimed is: 1. An apparatus for generating a substantially steady state positive voltage signal (PVS) and a substantially steady state negative voltage signal (NVS) to a switching module (SM), the PVS and the NVS remaining substantially stable during a switching event of the SM, including: a bias signal generation module (BSGM) for generating a substantially steady state reference voltage signal (RVS), the RVS having a voltage level nominally less than the PVS; a positive signal generation module (PSGM) generating the PVS, the PSGM including a first capacitor, the PSGM employing the first capacitor to nominally generate a portion of the PVS based on the RVS; and a negative signal generation module (NSGM) generating the NVS, the NSGM including a second capacitor, the NSGM employing the second capacitor to nominally generate a portion of the NVS based on the RVS. 2. The apparatus of claim 1 , wherein the SM modulates a radio frequency (RF) signal. 3. The apparatus of claim 1 , the PSGM generating a positive capacitor control signal (PCCS) based at least partially on the RVS and employing the first capacitor to nominally generate a portion of the PVS at least partially based on the PCCS. 4. The apparatus of claim 1 , the NSGM generating a negative capacitor control signal (NCCS) based at least partially on the RVS and employing the second capacitor to nominally generate a portion of the NVS at least partially based on the NCCS. 5. The apparatus of claim 1 , the BSGM employing a first FET element and a second FET element formed on a common silicon on insulator (SOI) wafer in part to generate the RVS where the RVS is temperature independent. 6. The apparatus of claim 3 , wherein the ratio of the PVS voltage magnitude to the RVS voltage magnitude is about 1.5 to 4. 7. A method of generating a substantially steady state positive voltage signal (PVS) and a substantially steady state negative voltage signal (NVS) to a switching module (SM), the PVS and the NVS remaining substantially stable during a switching event of the SM, including: generating a substantially steady state reference voltage signal (RVS), the RVS having a voltage level nominally less than the PVS; employing a first capacitor to nominally generate a portion of the PVS based on the RVS; and employing a second capacitor to nominally generate a portion of the NVS based on the RVS. 8. The method of claim 7 , wherein the SM modulates a radio frequency (RF) signal. 9. The method of claim 7 , further including generating a positive capacitor control signal (PCCS) based at least partially on the RVS and employing the first capacitor to nominally generate a portion of the PVS at least partially based on the PCCS. 10. The method of claim 9 , further including generating a negative capacitor control signal (NCCS) based at least partially on the RVS and employing the second capacitor to nominally generate a portion of the NVS at least partially based on the NCCS. 11. The method of claim 9 , wherein the ratio of the PVS voltage magnitude to the RVS voltage magnitude is about 1.5 to 4. 12. The method of claim 11 , wherein the ratio of the NVS voltage magnitude to the RVS voltage magnitude is about 1.5 to 4.

Assignees

Inventors

Classifications

  • using a switching device (H03F1/305, H03F3/005, H03F3/38 take precedence) · CPC title

  • G05F1/56Primary

    using semiconductor devices in series with the load as final control devices (G05F1/461 takes precedence) · CPC title

  • characterised by reference voltage circuitry, e.g. soft start, remote shutdown · CPC title

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Frequently asked questions

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What does patent US9778669B2 cover?
Embodiments of signal bias generators and regulators are described generally herein. Other embodiments may be described and claimed.
Who is the assignee on this patent?
Peregrine Semiconductor Corp
What technology area does this patent fall under?
Primary CPC classification G05F1/56. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Oct 03 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).