Resistive memory architectures with multiple memory cells per access device

Patent metadata

Field	Value
Publication number	US-9997701-B2
Application number	US-201615266859-A
Country	US
Kind code	B2
Filing date	Sep 15, 2016
Priority date	May 31, 2007
Publication date	Jun 12, 2018
Grant date	Jun 12, 2018

Abstract

A resistive memory structure, for example, phase change memory structure, includes one access device and two or more resistive memory cells. Each memory cell is coupled to a rectifying device to prevent parallel leak current from flowing through non-selected memory cells. In an array of resistive memory bit structures, resistive memory cells from different memory bit structures are stacked and share rectifying devices.

First claim

What is claimed is:

1. A memory device, comprising:
a first stacked memory structure including a first memory cell and a second memory cell;
an electrode positioned between the first memory cell and the second memory cell, the electrode operatively coupling the first memory cell and the second memory cell to a cell select line;
a first access device operatively coupled to the first memory cell; and
a second stacked memory structure including a third memory cell and a fourth memory cell, wherein the electrode is positioned between the third memory cell and the fourth memory cell and the electrode operatively couples the third memory cell and the fourth memory cell to the cell select line.

2. The memory device of claim 1 , further comprising:
a first rectifying device operatively coupled to the first memory cell and the first access device.

3. The memory device of claim 1 , further comprising:
a second access device operatively coupled to the second memory cell.

4. The memory device of claim 3 , further comprising:
a third rectifying device operatively coupled to the second memory cell and the second access device.

5. The memory device of claim 3 , wherein:
a position of the second access device is offset in a horizontal direction from the position of the first stacked memory structure.

6. The memory device of claim 1 , further comprising:
a second rectifying device operatively coupled to the electrode and the cell select line.

7. The memory device of claim 1 , wherein the first memory cell and the second memory cell each comprise a phase change memory cell.

8. The memory device of claim 1 , wherein the first memory cell and the second memory cell each comprise a resistive memory cell.

9. The memory device of claim 1 , wherein a top surface of the first memory cell is in contact with a first surface of the electrode and a top surface of the second memory cell is in contact with a second surface of the electrode different from the first surface.

10. The memory device of claim 1 ,
wherein the first access device is operatively coupled to the third memory cell.

11. A memory structure, comprising:
an access device configured to access a first memory cell in a first stacked memory structure and a second memory cell in a second stacked memory structure;
the first memory cell operatively coupled to the access device and a first cell access line;
the second memory cell operatively coupled to the access device and a second cell access line different from the first cell access line;
a first rectifying device operatively coupled to the first memory cell; and
a second rectifying device operatively coupled to the second memory cell.

12. The memory structure of claim 11 , wherein:
the first rectifying device is operatively coupled to the first memory cell and the access device; and
the second rectifying device is operatively coupled to the second memory cell and the access device.

13. The memory structure of claim 11 , wherein:
the first stacked memory structure comprises the first memory cell and a third memory cell; and
the second stacked memory structure comprises the second memory cell and a fourth memory cell.

14. The memory structure of claim 11 , wherein at least one of the first memory cell or the second memory cell comprises a phase change memory cell.

15. The memory structure of claim 11 , wherein at least one of the first memory cell or the second memory cell comprises a resistive memory cell.

16. The memory structure of claim 11 , wherein:
the first memory cell overlaps with the access device in a horizontal direction; and
the second memory cell is offset from the access device in the horizontal direction.

17. A memory device, comprising:
a stacked memory structure positioned at a first location, the stacked memory structure including a first memory cell and a second memory cell;
a first access device operatively coupled to the first memory cell, the first access device being positioned below the stacked memory structure in a vertical direction; and
a second access device operatively coupled to the second memory cell, the second access device being positioned at a second location different from the first location.

18. The memory device of claim 17 , further comprising:
a rectifying device operatively coupled to one of the memory cells of the stacked memory structure.

19. A memory device, comprising:
a stacked memory structure including a first memory cell and a second memory cell;
an electrode positioned between the first memory cell and the second memory cell, the electrode operatively coupling the first memory cell and the second memory cell to a cell select line;
an access device operatively coupled to the first memory cell; and
a rectifying device operatively coupled to the first memory cell and the access device.

20. A memory device, comprising:
a stacked memory structure including a first memory cell and a second memory cell;
an electrode positioned between the first memory cell and the second memory cell, the electrode operatively coupling the first memory cell and the second memory cell to a cell select line;
a first access device operatively coupled to the first memory cell; and
a second access device operatively coupled to the second memory cell, wherein a position of the second access device is offset in a horizontal direction from the position of the stacked memory structure.

21. A memory device, comprising:
a stacked memory structure including a first memory cell and a second memory cell;
an electrode positioned between the first memory cell and the second memory cell, the electrode operatively coupling the first memory cell and the second memory cell to a cell select line;
an access device operatively coupled to the first memory cell; and
a rectifying device operatively coupled to the electrode and the cell select line.

Assignees

• Ovonyx Memory Tech Llc

Inventors

• Liu Jun
• Violette Michael P

Classifications

• G11C13/0004 Primary

  comprising amorphous/crystalline phase transition cells · CPC title

• G11C13/0026

  Bit-line or column circuits · CPC title

• G11C13/003

  Cell access · CPC title

• G11C2213/79

  Array wherein the access device being a transistor · CPC title

• G11C2213/74

  Array wherein each memory cell has more than one access device · CPC title