Semiconductor device having magnetic tunnel junction structure and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-9997699-B2
Application number	US-201615158575-A
Country	US
Kind code	B2
Filing date	May 18, 2016
Priority date	Sep 18, 2015
Publication date	Jun 12, 2018
Grant date	Jun 12, 2018

Abstract

A semiconductor device and a method of forming the semiconductor device are disclosed. The semiconductor device includes a lower electrode and a magnetic tunnel junction structure disposed on the lower electrode. The magnetic tunnel junction structure includes a seed pattern disposed on the lower electrode. The seed pattern includes an amorphous seed layer and an oxidized seed layer disposed on a surface of the amorphous seed layer. The seed pattern may prevent the lattice structure of the lower electrode from adversely affecting the lattice structure of a pinned magnetic layer of the magnetic tunnel junction structure.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a seed pattern;
a pinned magnetic pattern disposed on the seed pattern;
a tunnel barrier pattern disposed on the pinned magnetic pattern; and
a free magnetic pattern disposed on the tunnel barrier pattern,
wherein the seed pattern includes a first amorphous seed layer, an oxidized seed layer disposed on a surface of the first amorphous seed layer, and a crystalline seed layer disposed on the oxidized seed layer, and
wherein the oxidized seed layer is disposed between the first amorphous seed layer and the crystalline seed layer.

2. The semiconductor device of claim 1 , wherein a side surface of the oxidized seed layer is substantially vertically aligned with a side surface of the first amorphous seed layer.

3. The semiconductor device of claim 1 , wherein the oxidized seed layer is disposed on the surface of the first amorphous seed layer proximate to the pinned magnetic pattern.

4. The semiconductor device of claim 3 , wherein a vertical thickness of the oxidized seed layer is less than a vertical thickness of the first amorphous seed layer.

5. The semiconductor device of claim 3 , wherein the seed pattern further includes a second amorphous seed layer disposed between the first amorphous seed layer and the oxidized seed layer, and wherein a configuration of the second amorphous seed layer is different from a configuration of the first amorphous seed layer.

6. The semiconductor device of claim 5 , wherein materials that form the oxidized seed layer include substantially all materials that form the second amorphous seed layer.

7. The semiconductor device of claim 5 , wherein a side surface of the second amorphous seed layer is substantially vertically aligned with a side surface of the oxidized seed layer.

8. The semiconductor device of claim 5 , wherein a vertical thickness of the second amorphous seed layer is less than a vertical thickness of the first amorphous seed layer.

9. The semiconductor device of claim 1 , wherein the oxidized seed layer includes an oxidized material of at least one material that forms the amorphous seed layer.

10. A semiconductor device, comprising:
a lower electrode;
an amorphous seed layer disposed on the lower electrode;
an oxidized seed layer disposed on and in direct contact with the amorphous seed layer;
a crystalline seed layer disposed on and in direct contact with the oxidized seed layer;
a pinned magnetic pattern disposed on and in direct contact with the crystalline seed layer;
a tunnel barrier pattern disposed on the pinned magnetic pattern; and
a free magnetic pattern disposed on the tunnel barrier pattern.

11. The semiconductor device of claim 10 , wherein the pinned magnetic pattern includes a lower pinned magnetic layer disposed in close proximity to the crystalline seed layer, an upper pinned magnetic layer disposed in close proximity to the tunnel barrier pattern, and a spacer disposed between the lower pinned magnetic layer and the upper pinned magnetic layer, and wherein a vertical thickness of the oxidized seed layer is less than a vertical thickness of the spacer.

12. The semiconductor device of claim 10 , wherein the oxidized seed layer includes at least one of material that forms the amorphous seed layer.

13. The semiconductor device of claim 10 , wherein a side surface of the oxidized seed layer is substantially vertically aligned with a side surface of the pinned magnetic pattern.

14. A semiconductor device, comprising:
a seed layer comprising a first layer and a second layer, the first layer comprising a first lattice structure and the second layer comprising a second lattice structure that is different from the first lattice structure;
a pinned magnetic layer on the second layer of the seed layer;
a tunnel barrier layer on the pinned magnetic layer; and
a free magnetic layer on the tunnel barrier pattern,
wherein the first layer comprises an amorphous lattice structure, and the second layer comprises a crystalline lattice structure,
wherein the seed layer further comprises a third layer between the first layer and the second layer, and
wherein a lattice structure of the third layer comprises an oxidized lattice structure of the amorphous lattice structure of the first layer.

15. The semiconductor device of claim 14 , wherein the third layer comprises an oxidized material of Ta or B.

16. The semiconductor device of claim 14 , wherein the third layer comprises a thickness of less than about 4 Å, and
wherein the thickness of the third layer is in a direction that is substantially parallel to a direction between the seed layer and the free magnetic layer.

17. The semiconductor device of claim 14 , further comprising a lower electrode, and
wherein the first layer of the seed layer is on the lower electrode.

18. The semiconductor device of claim 17 , further comprising an upper electrode on the free magnetic layer.

19. The semiconductor device of claim 18 , further comprising a capping layer and a hard mask layer between the free magnetic layer and the upper electrode.

Assignees

• Kim Juhyun
• Kim Kiwoong
• Oh Sechung
• Lim Woochang
• Samsung Electronics Co Ltd

Inventors

• Kim Juhyun
• Kim Kiwoong
• Oh Sechung
• Lim Woochang

Classifications

• H01L43/12 Primary

  Electricity · mapped topic

• H01L43/08

  Electricity · mapped topic

• H10N50/10

  Magnetoresistive devices · CPC title

• H10N50/01 Primary

  Manufacture or treatment · CPC title