FinFET resistor and method to fabricate same

Patent metadata

Field	Value
Publication number	US-9997590-B2
Application number	US-201615331998-A
Country	US
Kind code	B2
Filing date	Oct 24, 2016
Priority date	Oct 24, 2016
Publication date	Jun 12, 2018
Grant date	Jun 12, 2018

Abstract

A method includes providing a semiconductor substrate having a plurality of linear semiconductor fin structures spaced apart from one another on a surface of the substrate; siliciding sidewalls of the semiconductor fin structures; removing an unsilicided central portion of each semiconductor fin structure leaving, for a given one of the semiconductor fin structures, a pair of silicide fin structures that are parallel to one another and spaced apart from one another by a distance about equal to a width of the removed unsilicided central portion of the semiconductor fin structure; and forming contacts to conductively connect together a plurality of the silicide fin structures to form a resistor. A resistance value of the resistor is related at least to a type of silicide, a number of contacted adjacent silicide fin structures and a length between two contacts.

First claim

What is claimed is:

1. A structure, comprising:
a substrate having a top surface;
a dielectric layer disposed on the top surface; and
an array of linear resistive silicide fin structures extending upwardly perpendicular to the top surface and overlying a portion of a top surface of the dielectric layer, wherein individual ones of the linear resistive silicide fin structures are disposed parallel to one another;
where two adjacent linear resistive silicide fin structures also overly a portion of a Si fin stump that is disposed in and surrounded by the dielectric layer on the top surface of the substrate;
where linear resistive silicide fin structures of a pair of linear resistive silicide fin structures are spaced apart from one another by a distance about equal to a width of a removed unsilicided central portion of a precursor semiconductor fin structure, where the Si fin stump comprised a portion of the precursor semiconductor fin structure.

2. The structure as in claim 1 , further comprising a first electrically conductive contact disposed on at least two adjacent linear resistive silicide fin structures at a first location.

3. The structure as in claim 2 , further comprising a second electrically conductive contact disposed on the at least two adjacent linear resistive silicide fin structures at a second location that is spaced away from the first location by a predetermined length.

4. The structure as in claim 3 , where a resistor device is defined by the material of the linear resistive silicide fin structures between the first and second electrically conductive contacts, where a resistance value of the resistor device is related to a type of silicide, a number of contacted adjacent linear resistive silicide fin structures and the predetermined length.

5. The structure as in claim 4 , where the resistance value of the resistor device is further related to a height of the linear resistive silicide fin structures defined by a distance from the top surface of the layer of dielectric material to a top of the linear resistive silicide fin structures.

6. The structure as in claim 1 , where a two terminal resistor device is defined at least in part by at least two of the linear resistive silicide fin structures connected in parallel.

7. The structure as in claim 1 , where a two terminal resistor device is defined at least in part by at least two of the linear resistive silicide fin structures connected in series.

8. A structure, comprising:
a substrate having a top surface;
a dielectric layer disposed on the top surface; and
an array of linear resistive silicide fin structures extending upwardly perpendicular to the top surface and overlying a portion of a top surface of the dielectric layer, wherein individual ones of the linear resistive silicide fin structures are disposed parallel to one another;
where two adjacent linear resistive silicide fin structures also overly a portion of a Si fin stump that is disposed in and surrounded by the dielectric layer on the top surface of the substrate;
further comprising a first electrically conductive contact disposed on at least two adjacent linear resistive silicide fin structures at a first location;
further comprising a second electrically conductive contact disposed on the at least two adjacent linear resistive silicide fin structures at a second location that is spaced away from the first location by a predetermined length;
where a resistor device is defined by the material of the linear resistive silicide fin structures between the first and second electrically conductive contacts, where a resistance value of the resistor device is related to a type of silicide, a number of contacted adjacent linear resistive silicide fin structures and the predetermined length.

9. The structure as in claim 8 , where the resistance value of the resistor device is further related to a height of the linear resistive silicide fin structures defined by a distance from the top surface of the layer of dielectric material to a top of the linear resistive silicide fin structures.

10. The structure as in claim 8 , where linear resistive suicide fin structures of a pair of linear resistive silicide fin structures are spaced apart from one another by a distance about equal to a width of a removed unsilicided central portion of a precursor semiconductor fin structure, where the Si fin stump comprised a portion of the precursor semiconductor fin structure.

11. The structure as in claim 8 , where a two terminal resistor device is defined at least in part by at least two of the linear resistive silicide fin structures connected in parallel.

12. The structure as in claim 8 , where a two terminal resistor device is defined at least in part by at least two of the linear resistive silicide fin structures connected in series.

Assignees

• IBM
• Int Buesiness Machines Corporation

Inventors

• Adusumilli Praneet
• Fogel Keith E
• Reznicek Alexander
• Van Der Straten Oscar

Classifications

• H01L27/1211

  Electricity · mapped topic

• H01L29/785

  Electricity · mapped topic

• H01L28/24 Primary

  Electricity · mapped topic

• H01L27/0802

  Electricity · mapped topic

• H10D84/811

  Combinations of field-effect devices and one or more diodes, capacitors or resistors · CPC title