High density resistive random access memory (RRAM)

Patent metadata

Field	Value
Publication number	US-9305974-B1
Application number	US-201514688597-A
Country	US
Kind code	B1
Filing date	Apr 16, 2015
Priority date	Apr 16, 2015
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

A resistive random access memory (RRAM) structure is formed on a supporting substrate and includes a first electrode and a second electrode. The first electrode is made of a silicided fin on the supporting substrate and a first metal liner layer covering the silicided fin. A layer of dielectric material having a configurable resistive property covers at least a portion of the first metal liner. The second electrode is made of a second metal liner layer covering the layer of dielectric material and a metal fill in contact with the second metal liner layer. A non-volatile memory cell includes the RRAM structure electrically connected between an access transistor and a bit line.

First claim

What is claimed is:

1. A non-volatile integrated circuit memory cell, comprising:
a supporting substrate;
a resistive random access memory structure comprising:
a first electrode, comprising:
a silicided semiconductor fin on said supporting substrate; and
a first metal liner layer covering said silicided semiconductor fin; and

a layer of dielectric material having a configurable resistive property and covering at least a portion of said first metal liner; and
a second electrode, comprising:
a second metal liner layer covering said layer of dielectric material; and
a metal fill in contact with the second metal liner layer;

a transistor having a first source-drain terminal connected to one of the first and second electrodes;
a source line connected to a second source-drain terminal of the transistor;
a word line connected to a gate terminal of the transistor; and
a bit line connected to another of the first and second electrodes.

2. The non-volatile integrated circuit memory cell of claim 1 , wherein said supporting substrate is of a silicon on insulator (SOI) type.

3. The non-volatile integrated circuit memory cell of claim 2 , said SOI type substrate having a semiconductor layer, and wherein said silicided semiconductor fin is formed from said semiconductor layer.

4. The non-volatile integrated circuit memory cell of claim 1 , wherein said supporting substrate is of a bulk substrate type.

5. The non-volatile integrated circuit memory cell of claim 4 , wherein said silicided semiconductor fin is formed from a portion of said bulk substrate.

6. The non-volatile integrated circuit memory cell of claim 1 , further comprising sidewall spacers on each side of the first metal liner layer on an upper portion of the silicided semiconductor fin.

7. The non-volatile integrated circuit memory cell of claim 1 , further comprising:
a premetallization dielectric layer;
a first contact extending through the premetallization dielectric layer to electrically connect to the metal fill; and
a second contact extending through the premetallization dielectric layer to electrically connect to the first metal liner layer at a top surface of the silicided semiconductor fin.

8. The non-volatile integrated circuit memory cell of claim 1 , wherein the resistive random access memory structure further comprises:
an additional silicided semiconductor fin on said supporting substrate, said first metal liner layer further covering said additional silicided semiconductor fin;
said layer of dielectric material further covering at least a portion of said first metal liner at the additional silicided semiconductor fin;
said second metal liner layer covering said layer of dielectric material at the additional silicided semiconductor fin; and
said metal fill in contact with the second metal liner layer being positioned between the silicided semiconductor fin and the additional silicided semiconductor fin.

9. The non-volatile integrated circuit memory cell of claim 1 , wherein the layer of dielectric material is made of hafnium oxide.

10. A resistive random access memory (RRAM) structure, comprising:
a supporting substrate;
a first electrode, comprising:
a silicided semiconductor fin on said supporting substrate; and
a first metal liner layer covering said silicided semiconductor fin;

a layer of dielectric material having a configurable resistive property and covering at least a portion of said first metal liner; and
a second electrode, comprising:
a second metal liner layer covering said layer of dielectric material; and
a metal fill in contact with the second metal liner layer.

11. The RRAM structure of claim 10 , wherein said supporting substrate is of a silicon on insulator (SOI) type.

12. The RRAM structure of claim 11 , said SOI type substrate having a semiconductor layer, and wherein said silicided semiconductor fin is formed from said semiconductor layer.

13. The RRAM structure of claim 10 , wherein said supporting substrate is of a bulk substrate type.

14. The RRAM structure of claim 13 , wherein said silicided semiconductor fin is formed from a portion of said bulk substrate.

15. The RRAM structure of claim 10 , further comprising:
an additional silicided semiconductor fin on said supporting substrate, said first metal liner layer further covering said additional silicided semiconductor fin;
said layer of dielectric material further covering at least a portion of said first metal liner at the additional silicided semiconductor fin;
said second metal liner layer covering said layer of dielectric material at the additional silicided semiconductor fin; and
said metal fill in contact with the second metal liner layer being positioned between the silicided semiconductor fin and the additional silicided semiconductor fin.

16. The RRAM structure of claim 10 , wherein the layer of dielectric material is made of hafnium oxide.

17. The RRAM structure of claim 10 , wherein the silicided semiconductor fin comprises a fully-silicided semiconductor structure.

18. A non-volatile integrated circuit memory cell, comprising:
a supporting substrate;
a resistive random access memory structure comprising:
a first electrode, comprising:
a fin that is a fully-silicided semiconductor structure on said supporting substrate; and
a first metal liner layer covering said fin; and

a layer of dielectric material having a configurable resistive property and covering at least a portion of said first metal liner; and
a second electrode, comprising:
a second metal liner layer covering said layer of dielectric material; and
a metal fill in contact with the second metal liner layer;

a transistor having a first source-drain terminal connected to one of the first and second electrodes;
a source line connected to a second source-drain terminal of the transistor;
a word line connected to a gate terminal of the transistor; and
a bit line connected to another of the first and second electrodes.

19. The non-volatile integrated circuit memory cell of claim 18 , wherein said supporting substrate is of a silicon on insulator (SOI) type.

20. The non-volatile integrated circuit memory cell of claim 19 , said SOI type substrate having a semiconductor layer, and wherein said fin is formed from said semiconductor layer.

21. The non-volatile integrated circuit memory cell of claim 18 , wherein said supporting substrate is of a bulk substrate type.

22. The non-volatile integrated circuit memory cell of claim 21 , wherein said fin is formed from a portion of said bulk substrate.

23. The non-volatile integrated circuit memory cell of claim 18 , further comprising sidewall spacers on each side of the first metal liner layer on an upper portion of the fin.

24. The non-volatile integrated circuit memory cell of claim 18 , further comprising:
a premetallization dielectric layer;
a first contact extending through the premetallization dielectric layer to electrically connect to the metal fill; and
a second contact extending through the premetallization dielectric layer to electrically connect to the first metal liner layer at a top surface of the fin.

25. The non-volatile integrated circuit memory cell of claim 18 , wherein the resistive random access memory structure further comprises:
an additional fin that is a fully-silicided semiconductor structure on said supporting substrate, said first metal liner layer further cove

Assignees

• St Microelectronics Inc

Inventors

• Liu Qing
• Zhang John Hongguang

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• G11C13/0002

  using resistive RAM [RRAM] elements · CPC title

• H01L45/1253

  Electricity · mapped topic

• H01L45/145

  Electricity · mapped topic

• H01L27/2436 Primary

  Electricity · mapped topic