Nonvolatile semiconductor storage device and method of manufacture thereof

Patent metadata

Field	Value
Publication number	US-8952439-B2
Application number	US-201213607508-A
Country	US
Kind code	B2
Filing date	Sep 7, 2012
Priority date	Mar 23, 2012
Publication date	Feb 10, 2015
Grant date	Feb 10, 2015

Abstract

A nonvolatile semiconductor storage device includes a semiconductor substrate on which an element isolation groove is formed, memory cells each including a gate electrode having a charge storage layer, an interelectrode insulating film, and a control electrode, that is formed on the semiconductor substrate via a tunnel insulating film, and an insulating film disposed in the element isolation groove. The interelectrode insulating film is formed to have a first portion above the insulating film that is separated from one of the insulating film and the control electrode by an air gap and a second portion above the charge storage layer that is separated from the charge storage layer by a cavity.

First claim

What is claimed is:

1. A nonvolatile semiconductor storage device, comprising:
a semiconductor substrate having an element isolation groove;
a plurality of memory cells, each including a first gate electrode having a charge storage layer, an interelectrode insulating film, and a control electrode, the first gate electrode being on the semiconductor substrate via a tunnel insulating film, and the interelectrode insulating film being between the charge storage layer and the control electrode; and
an insulating film in the element isolation groove, the insulating film having an upper surface that is lower than an upper surface of the semiconductor substrate,
wherein the interelectrode insulating film and the control electrode of the first gate electrode are over the insulating film, and the interelectrode insulating film includes a first portion directly on the insulating film and a second portion over the charge storage layer that is separated from the charge storage layer by a cavity.

2. The nonvolatile semiconductor storage device according to claim 1 , further comprising:
a peripheral transistor including a gate electrode having a first electrode, an interelectrode insulating film, and a second electrode that is on the semiconductor substrate via a gate insulating film, wherein the first electrode is the same layer as the charge storage layer of the memory cells and the second electrode is the same layer as the control electrode of the memory cells.

3. The nonvolatile semiconductor storage device according to claim 2 , wherein the interelectrode insulating film of the peripheral transistor is formed directly on an insulating film disposed in an element isolation groove at the side of the second gate electrode, and the second electrode is directly on the interelectrode insulating film of the peripheral transistor.

4. The nonvolatile semiconductor storage device according to claim 3 , wherein the interelectrode insulating film of the peripheral transistor comprises an oxide film and has a portion facing a gap.

5. The nonvolatile semiconductor storage device according to claim 4 , wherein the interelectrode insulating film of the peripheral transistor is provided with a nitride film that is formed by a plasma nitrification treatment.

6. A nonvolatile semiconductor storage device, comprising:
a semiconductor substrate having an element isolation groove;
a plurality of memory cells, each including a gate electrode having a charge storage layer, an interelectrode insulating film, and a control electrode, the gate electrode being on the semiconductor substrate via a tunnel insulating film, and the interelectrode insulating film being between the charge storage layer and the control electrode; and
an insulating film in the element isolation groove,
wherein the interelectrode insulating film and the control electrode of the gate electrode are over the element isolation groove, and the interelectrode insulating film includes a portion directly on the insulating film between the control electrode and the insulating film that is separated from the control electrode by a gap.

7. The nonvolatile semiconductor storage device according to claim 6 , wherein an upper surface of the insulating film is lower than an upper surface of the semiconductor substrate.

8. The nonvolatile semiconductor storage device according to claim 6 , wherein the interelectrode insulating film has a portion above the charge storage layer that is separated from the charge storage layer by a cavity.

9. The nonvolatile semiconductor storage device according to claim 6 , further comprising:
a peripheral transistor including a gate electrode having a first electrode, an interelectrode insulating film, and a second electrode that is on the semiconductor substrate via a gate insulating film, wherein the first electrode is the same layer as the charge storage layer of the memory cells and the second electrode is same layer as the control electrode of the memory cells.

10. The nonvolatile semiconductor storage device according to claim 9 , wherein the interelectrode insulating film of the peripheral transistor is directly on an insulating film disposed in an element isolation groove at the side of the second gate electrode, and the second electrode is directly on the interelectrode insulating film of the peripheral transistor.

11. The nonvolatile semiconductor storage device according to claim 10 , wherein the interelectrode insulating film of the peripheral transistor comprises an oxide film and has a portion facing the gap.

12. The nonvolatile semiconductor storage device according to claim 11 , wherein the interelectrode insulating film of the peripheral transistor is provided with a nitride film that is formed by a plasma nitrification treatment.

Assignees

• Suzuki Ryota
• Toshiba Kk

Inventors

• Suzuki Ryota

Classifications

• H10W10/021

  of air gaps · CPC title

• H10W10/20

  Air gaps · CPC title

• H10D62/122

  oriented at angles to substrates, e.g. perpendicular to substrates · CPC title

• H10D64/035

  comprising conductor-insulator-conductor-insulator-semiconductor structures · CPC title

• H10D30/681

  having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D30/688) · CPC title