Semiconductor package with stacked semiconductor chips

Patent metadata

Field	Value
Publication number	US-9997481-B2
Application number	US-201213628549-A
Country	US
Kind code	B2
Filing date	Sep 27, 2012
Priority date	May 11, 2012
Publication date	Jun 12, 2018
Grant date	Jun 12, 2018

Abstract

A semiconductor package includes a build-up structure; a semiconductor disposed on the build-up structure in a flip-chip manner and having a plurality of bumps penetrating therethrough; an electronic element disposed on the semiconductor chip; and an encapsulant formed on the build-up structure and encapsulating the semiconductor chip and the electronic element, thereby improving the product yield and the overall heat dissipating efficiency.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a build-up structure having a plurality of conductive pads exposed from a top surface thereof;
a first semiconductor chip disposed on the top surface of the build-up structure in a flip-chip manner, wherein the first semiconductor chip has a first active surface and a first non-active surface opposite to the first active surface, the first active surface has a plurality of first electrode pads electrically connected to the conductive pads, respectively, and a plurality of first through holes are formed in the first semiconductor chip via the first non-active surface thereof such that a plurality of first bumps made of solder are integrally formed in the first through holes and electrically connected to the first electrode pads;
an electronic element disposed on the first semiconductor chip and electrically connected to the first bumps, wherein a copper pillar and a solder material are formed between the electronic element and the first bumps, the copper pillar is attached to the electronic element and the solder material, and the solder material is attached to and in direct contact with the copper pillar and the first bumps such that the solder material and the first bumps are integrally formed; and
an encapsulant formed on the top surface of the build-up structure for encapsulating the first semiconductor chip and the electronic element.

2. The semiconductor package of claim 1 , wherein the first electrode pads are exposed from the first through holes, respectively.

3. The semiconductor package of claim 1 , wherein a circuit layer that is electrically connected to the first electrode pads is exposed through the first through holes.

4. The semiconductor package of claim 1 , wherein the first bumps are made of Ni, Sn, Ag, Cu, Pd, Au, Al or a combination thereof.

5. The semiconductor package of claim 1 , wherein the build-up structure has a plurality of bonding pads exposed from a bottom surface thereof.

6. The semiconductor package of claim 1 , wherein the electronic element is a semiconductor chip, a passive component or a semiconductor package.

7. The semiconductor package of claim 1 , wherein each of the conductive pads further comprises a conductive layer and a first solder material sequentially formed thereon.

8. The semiconductor package of claim 1 , wherein the encapsulant further comprises a first body encapsulating the first semiconductor chip and a second body encapsulating the electronic element.

9. The semiconductor package of claim 1 , further comprising a second semiconductor chip disposed between the first semiconductor chip and the electronic element.

10. The semiconductor package of claim 1 , wherein a circuit layer is further formed on the first non-active surface of the first semiconductor chip and electrically connected to the first bumps.

11. A semiconductor package, comprising:
a carrier having a plurality of conductive pads exposed from a top surface thereof;
a first semiconductor chip disposed on the top surface of the carrier in a flip-chip manner, wherein the first semiconductor chip has a first active surface and a first non-active surface opposite to the first active surface, the first active surface has a plurality of first electrode pads electrically connected to the conductive pads, respectively, and a plurality of first through holes are formed in the first semiconductor chip via the first non-active surface thereof such that a plurality of first bumps made of solder are integrally formed in the first through holes and electrically connected to the first electrode pads, and a heat conducting layer is further formed on the first non-active surface of the first semiconductor chip;
an electronic element disposed on the first semiconductor chip and electrically connected to the first bumps, wherein a copper pillar and a solder material are formed between the electronic element and the first bumps, the copper pillar is attached to the electronic element and the solder material, and the solder material is attached to and in direct contact with the copper pillar and the first bumps such that the solder material and the first bumps are integrally formed; and
an encapsulant formed on the top surface of the carrier for encapsulating the first semiconductor chip and the electronic element while exposing an edge of the heat conducting layer.

12. The semiconductor package of claim 11 , wherein the first electrode pads are exposed through the first through holes, respectively.

13. The semiconductor package of claim 11 , wherein a circuit layer that is electrically connected to the first electrode pads is exposed through the first through holes.

14. The semiconductor package of claim 11 , wherein the first bumps are made of Ni, Sn, Ag, Cu, Pd, Au, Al or a combination thereof.

15. The semiconductor package of claim 11 , wherein the electronic element is a semiconductor chip, a passive component or a semiconductor package.

16. The semiconductor package of claim 11 , wherein the carrier is a circuit board or a packaging substrate.

17. The semiconductor package of claim 11 , wherein the encapsulant further comprises a first body encapsulating the first semiconductor chip and a second body encapsulating the electronic element.

18. The semiconductor package of claim 11 , further comprising a second semiconductor chip disposed between the first semiconductor chip and the electronic element.

19. The semiconductor package of claim 11 , wherein a circuit layer is further formed on the first non-active surface of the first semiconductor chip and electrically connected to the first bumps.

Assignees

• Siliconware Precision Industries Co Ltd

Inventors

• Chen Lu-Yi

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title

• H10W20/0261

  characterised by the filling method or the material of the conductive fill · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title