Semiconductor memory devices

Patent metadata

Field	Value
Publication number	US-9997462-B2
Application number	US-201715581782-A
Country	US
Kind code	B2
Filing date	Apr 28, 2017
Priority date	Oct 28, 2016
Publication date	Jun 12, 2018
Grant date	Jun 12, 2018

Abstract

A memory device includes a vertical string of nonvolatile memory cells on a substrate, along with a ground selection transistor extending between the vertical string of nonvolatile memory cells and the substrate. The ground selection transistor can have a current carrying terminal electrically coupled to a channel region of a nonvolatile memory cell in the vertical string of nonvolatile memory cells. The ground selection transistor includes a gate electrode associated with a ground selection line of the memory device. This gate electrode includes: (i) a mask pattern, (ii) a barrier metal layer of a first material extending opposite a sidewall of the mask pattern and (iii) a metal pattern of a second material different from the first material extending between at least a portion of the barrier metal layer and the mask pattern.

First claim

What is claimed is:

1. A memory device, comprising:
a vertical string of nonvolatile memory cells on a substrate; and
a ground selection transistor extending between said vertical string of nonvolatile memory cells and the substrate, said ground selection transistor having a current carrying terminal electrically coupled to a channel region of a nonvolatile memory cell in said vertical string of nonvolatile memory cells, said ground selection transistor comprising a gate electrode associated with a ground selection line of the memory device and said gate electrode comprising (i) a mask pattern, (ii) a barrier metal layer of a first material extending opposite a sidewall of the mask pattern and (iii) a metal pattern of a second material different from the first material extending between at least a portion of the barrier metal layer and the mask pattern.

2. The memory device of claim 1 , wherein said gate electrode of said ground selection transistor is an insulated gate electrode; and wherein the mask pattern comprises a third material different from the second material.

3. The memory device of claim 2 , wherein the mask pattern comprises an electrically insulating material.

4. The memory device of claim 2 , wherein the mask pattern comprises an electrically conductive material selected from a group consisting of WN, TaN, TiSiN, Co, Ni, Ti, Ta, WSix and TiSix.

5. The memory device of claim 4 , wherein the barrier metal layer comprises a metal nitride layer; and wherein the metal pattern comprises tungsten (W).

6. The memory device of claim 5 , wherein the barrier metal layer wraps around a sidewall of the metal pattern and extends onto top and bottom surfaces of the metal pattern; and wherein the metal pattern wraps around a sidewall of the mask pattern and extends onto top and bottom surfaces of the mask pattern.

7. The memory device of claim 6 , wherein the mask pattern comprises an electrically insulating material.

8. A semiconductor memory device, comprising:
a stack structure on a substrate, the stack structure including a ground select line and word lines stacked on the ground select line; and
a vertical channel on the substrate and penetrating the stack structure,
wherein the ground select line comprises:
a first mask pattern;
a first barrier pattern extending onto top and bottom surfaces of the first mask pattern from between the vertical channel and the first mask pattern; and
a first metal pattern between the first mask pattern and the first barrier pattern.

9. The semiconductor memory device of claim 8 , wherein the first metal pattern comprises a recession recessed toward the vertical channel, the first mask pattern being provided in the recession.

10. The semiconductor memory device of claim 8 , wherein the ground select line has a thickness greater than that of each of the word lines.

11. The semiconductor memory device of claim 8 , wherein each of the word lines comprises:
a second metal pattern; and
a second barrier pattern extending onto top and bottom surfaces of the second metal pattern from between the vertical channel and the second metal pattern,
the first and second metal patterns having the same material.

12. The semiconductor memory device of claim 8 , wherein the first mask pattern comprises a conductive material having an etch selectivity to the first metal pattern.

13. The semiconductor memory device of claim 8 , wherein the first mask pattern comprises an insulating material.

14. The semiconductor memory device of claim 8 , wherein the first mask pattern has a sidewall exposed through the first barrier pattern, the sidewall of the first mask pattern being concave.

15. The semiconductor memory device of claim 8 , wherein
the stack structure further comprises insulation patterns between the ground select line and its adjacent one word line and between the word lines adjacent to each other, and
the semiconductor memory device further comprises a contact structure disposed on the substrate on a side of the stack structure, the contact structure comprising,
a contact plug; and
a spacer between the contact plug and the stack structure,

wherein the ground select line and the word lines have sidewalls recessed toward the vertical channel from sidewalls of the insulation patterns, and
wherein the spacer fills a space between the insulation patterns adjacent to each other.

16. The semiconductor memory device of claim 8 , wherein the stack structure further comprises a string select line on the word lines,
wherein the string select line comprises:
a second mask pattern;
a second barrier pattern extending onto top and bottom surfaces of the second mask pattern from between the vertical channel and the second mask pattern; and
a second metal pattern extending onto top and bottom surfaces of the second mask pattern from between the second mask pattern and the second barrier pattern.

17. A semiconductor memory device, comprising:
a stack structure on a substrate, the stack structure including a ground select line and word lines stacked the ground select line; and
a vertical channel on the substrate and penetrating the stack structure,
wherein the ground select line comprises:
a mask pattern; and
a first metal pattern extending onto top and bottom surfaces of the mask pattern from between the vertical channel and the mask pattern,

wherein each of the word lines comprises:
a second metal pattern; and
a barrier pattern extending onto top and bottom surfaces of the second metal pattern from between the vertical channel and the second metal pattern,

wherein the first and second metal patterns have the same material.

18. The semiconductor memory device of claim 17 , wherein the mask pattern comprises a conductive material having an etch selectivity to the first metal pattern.

19. The semiconductor memory device of claim 17 , wherein the mask pattern comprises an insulating material.

20. The semiconductor memory device of claim 17 , wherein the ground select line has a thickness greater than that of each of the word lines.

Assignees

• Ha Jooyeon
• Lee Jeonggil
• Kim Dohyung
• Lee Keun
• Lim Hyunseok
• Han Hauk
• Samsung Electronics Co Ltd

Inventors

• Ha Jooyeon
• Lee Jeonggil
• Kim Dohyung
• Lee Keun
• Lim Hyunseok
• Han Hauk

Classifications

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/20 Primary

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H01L27/11578

  Electricity · mapped topic

• H01L29/7926

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic