Vertical type semiconductor devices and methods of manufacturing the same
US-2024172441-A1 · May 23, 2024 · US
Non-volatile memory device having a vertical structure and method of fabricating the same
US8994091B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8994091-B2 |
| Application number | US-201213458293-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 27, 2012 |
| Priority date | May 3, 2011 |
| Publication date | Mar 31, 2015 |
| Grant date | Mar 31, 2015 |
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Abstract
Official abstract text for this publication.
A non-volatile memory device having a vertical structure includes a semiconductor layer, a sidewall insulation layer extending in a vertical direction on the semiconductor layer, and having one or more protrusion regions, first control gate electrodes arranged in the vertical direction on the semiconductor layer, and respectively contacting one of portions of the sidewall insulation layer where the one or more protrusion regions are not formed and second control gate electrodes arranged in the vertical direction on the semiconductor layer, and respectively contacting one of the one or more protrusion regions.
First claim
Opening claim text (preview).
What is claimed is: 1. A non-volatile memory device having a vertical structure, the non-volatile memory device comprising: a semiconductor layer; a sidewall insulation layer extending in a vertical direction on the semiconductor layer, and having one or more protrusion regions; a plurality of first control gate electrodes arranged in the vertical direction on the semiconductor layer; and a plurality of second control gate electrodes arranged in the vertical direction on the…
Assignees
Inventors
Classifications
Electricity · mapped topic
- H10D30/689Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H01L27/11556Primary
Electricity · mapped topic
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- What does patent US8994091B2 cover?
- A non-volatile memory device having a vertical structure includes a semiconductor layer, a sidewall insulation layer extending in a vertical direction on the semiconductor layer, and having one or more protrusion regions, first control gate electrodes arranged in the vertical direction on the semiconductor layer, and respectively contacting one of portions of the sidewall insulation layer where…
- Who is the assignee on this patent?
- Lee Sang-Hoon, Kim Jin-Gyun, Nam Koong-Hyun, and 4 more
- What technology area does this patent fall under?
- Primary CPC classification H10D30/689. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 31 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).