Semiconductor package including a rewiring layer with an embedded chip

Patent metadata

Field	Value
Publication number	US-9997446-B2
Application number	US-201715468294-A
Country	US
Kind code	B2
Filing date	Mar 24, 2017
Priority date	Aug 5, 2016
Publication date	Jun 12, 2018
Grant date	Jun 12, 2018

Abstract

A semiconductor package includes a substrate, a rewiring layer, a plurality of semiconductor chip stack structures, and a second semiconductor chip. The rewiring layer is disposed on an upper surface of the substrate. The rewiring layer includes a concave portion. The semiconductor chip stack structures include a plurality of first semiconductor chips. The first semiconductor chips are disposed on the rewiring layer. The first semiconductor chips are spaced apart from each other in a horizontal direction. The second semiconductor chip is disposed within the concave portion. The second semiconductor chip is configured to electrically connect each of the plurality of semiconductor chip stack structures to each other.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a substrate;
a rewiring layer disposed on an upper surface of the substrate, the rewiring layer comprising a concave portion and a first wiring;
a plurality of semiconductor chip stack structures comprising a plurality of first semiconductor chips disposed on the rewiring layer and spaced apart from each other in a horizontal direction; and
a second semiconductor chip disposed within the concave portion and including a second wiring,
wherein the second semiconductor chip is configured to electrically connect each of the plurality of semiconductor chip stack structures to each other, and
wherein a line width of the first wiring is greater than a line width of the second wiring.

2. The semiconductor package of claim 1 , wherein the concave portion is disposed in a surface of the rewiring layer facing the first semiconductor chips.

3. The semiconductor package of claim 1 , wherein the concave portion penetrates into the rewiring layer.

4. The semiconductor package of claim 1 , further comprising an adhesion member disposed in the concave portion, wherein the adhesion member attaches the rewiring layer to the second semiconductor chip.

5. The semiconductor package of claim 4 , wherein the second semiconductor chip is an active element.

6. The semiconductor package of claim 5 , further comprising:
a plurality of first connection terminals disposed between the rewiring layer and the substrate;
a plurality of second connection terminals disposed between the rewiring layer and the semiconductor chip stack structures; and
a plurality of third connection terminals disposed between the second semiconductor chip and the semiconductor chip stack structures,
wherein the first connection terminals are larger than the second connection terminals.

7. The semiconductor package of claim 6 , wherein the second connection terminals are larger than the third connection terminals.

8. The semiconductor package of claim 6 , further comprising:
a plurality of first connection pads arranged on a surface of the rewiring layer facing the substrate and electrically connected to the first connection terminals;
a plurality of second connection pads arranged on a surface of the rewiring layer facing the semiconductor chip stack structures and electrically connected to the second connection terminals; and
a plurality of third connection pads arranged on a surface of the second semiconductor chip facing the semiconductor chip stack structures and electrically connected to the third connection terminals,
wherein the first connection pads are larger than the second connection pads.

9. The semiconductor package of claim 8 , wherein the second connection pads are larger than the third connection pads.

10. The semiconductor package of claim 1 , wherein the line width of the second wiring is less than about 2 μm.

11. A semiconductor package, comprising:
a substrate formed at a first level;
a plurality of semiconductor chip stack structures formed at a third level and spaced apart from each other in a horizontal direction;
a first rewiring layer formed at a second level, the second level disposed between the first level and the third level and electrically connecting the substrate and at least one of the semiconductor chip stack structures and the first rewiring layer including a first wiring; and
a bridge layer formed at the second level and electrically connecting at least one of the semiconductor chip stack structures and including a second wiring,
wherein a line width of the first wiring is greater than a line width of the second wiring.

12. The semiconductor package of claim 11 , wherein the bridge layer is disposed within the first rewiring layer.

13. The semiconductor package of claim 11 , further comprising a second rewiring layer formed at the second level, wherein the second rewiring layer is spaced apart from the first rewiring layer, and electrically connects the substrate and at least one of the semiconductor chip stack structures.

14. The semiconductor package of claim 13 , wherein the bridge layer is disposed between the first rewiring layer and the second rewiring layer.

15. A semiconductor package, comprising:
a substrate;
a rewiring layer disposed on the substrate, the rewiring layer comprising a concave portion and a first wiring;
a plurality of semiconductor chip stack structures disposed on the rewiring layer; and
a second semiconductor chip disposed within the concave portion and including a second wiring,
wherein the second semiconductor chip is configured to electrically connect the semiconductor chip stack structures to each other, and
wherein a line width of the first wiring is greater than a line width of the second wiring.

16. The semiconductor package of claim 15 , wherein the concave portion is disposed in a surface of the rewiring layer facing the semiconductor chip stack structures.

17. The semiconductor package of claim 15 , wherein the concave portion penetrates into the rewiring layer.

18. The semiconductor package of claim 15 , further comprising an adhesion member disposed in the concave portion, wherein the adhesion member attaches the rewiring layer to the second semiconductor chip.

19. The semiconductor package of claim 15 , wherein a horizontal cross-sectional area of the second semiconductor chip is smaller than a horizontal cross-sectional area of the concave portion.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Ji-Hwang
• Shim Jong-Bo
• Jo Cha-Jea
• Lee Won-Il

Classifications

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W70/655

  Fan-out layouts · CPC title

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title