Repair circuit and semiconductor memory device including the same

Patent metadata

Field	Value
Publication number	US-9230693-B1
Application number	US-201514688789-A
Country	US
Kind code	B1
Filing date	Apr 16, 2015
Priority date	Dec 8, 2014
Publication date	Jan 5, 2016
Grant date	Jan 5, 2016

Abstract

A repair circuit includes a test data processing unit that outputs first and second fail detection signals using first and second test data of first and second memory banks, respectively, in response to a test mode signal, a repair address control unit that sets a priority of the first and second memory banks and selectively stores first and second addresses of the first and second memory banks based on the set priority in response to the first and second fail detection signals, and a fuse unit that performs repair programming based on the addresses selectively stored in the repair address control unit.

First claim

What is claimed:

1. A repair circuit comprising:
a test data processing unit suitable for outputting first and second fail detection signals using first and second test data of first and second memory banks, respectively, in response to a test mode signal;
a repair address control′ unit suitable for setting a priority of the first and second memory banks and selectively storing first and second addresses of the first and second memory banks based on the set priority in response to the first and second fail detection signals; and
a fuse unit suitable for performing repair programming based on the addresses selectively stored in the repair address control unit.

2. The repair circuit of claim 1 , herein the repair address control unit comprises:
an output control section suitable for selectively outputting the first and second addresses based on the set priority in response to the first and second fail detection signals; and
a latch section suitable for latching the address selectively outputted from the output control section.

3. The repair circuit of claim 1 , wherein the test data processing unit combines the first and second test data and outputs the first and second fail detection signals, respectively, in response to the test mode signal.

4. The repair circuit of claim 3 , wherein, when failures occur in the first test data, the test data processing unit activates the first fail detection signal, and when failures occur in the second test data, the test data processing unit activates the second fail detection signal.

5. The repair circuit of claim 1 , wherein the fuse unit programs the addresses selectively stored in the repair address control unit as repair address information in response to a rupture enable signal.

6. The repair circuit of claim 1 , further comprising:
a test mode setting unit suitable for generating an additional test operation signal in response to the test mode signal when all the first and second fail detection signals are activated.

7. The repair circuit of claim 6 , wherein the additional test operation signal includes a signal for additionally performing a test operation which is performed in response to the test mode signal.

8. The repair circuit of claim 1 , wherein the test mode signal includes a signal for performing a self-address rupture operation of the first and second memory banks.

9. The repair circuit of claim 1 , wherein the fuse unit includes a fuse set corresponding to the first and second memory banks.

10. The repair circuit of claim 1 , further comprising:
a plurality of memory bank groups includes the first and second memory banks.

11. The repair circuit of claim 10 , wherein, when failure occurs in one or more of a plurality of pieces of test data outputted from the plurality of memory banks groups, the test data processing unit outputs the fail detection signal corresponding to the failed test data in response to the test mode signal.

12. The repair circuit of claim 11 , wherein the repair address control unit suitable for setting a priority of the plurality of memory bank groups and selectively storing the address based on the set priority in response to the plurality of fail detection signals.

13. A method of operating a repair circuit, comprising:
setting a priority of first and second memory banks;
performing a test operation on the first and second memory banks to generate first and second fail detection signals, respectively;
selectively storing first and second addresses of the first and second memory banks based on the set priority in response to the first and second fail detection signals; and
programming the selectively stored addresses.

14. The method of claim 13 , wherein the performing of the test operation includes:
combining first and second test data outputted from the first and second memory banks; and
detecting whether a failure occurs in the first and second memory banks using the combined first and second test data, respectively.

Assignees

• Sk Hynix Inc

Inventors

• Lee Joo-Hyeon

Classifications

• G11C29/04

  Detection or location of defective memory elements {, e.g. cell constructio details, timing of test signals} · CPC title

• G11C29/78 Primary

  using programmable devices · CPC title

• G11C17/18

  Auxiliary circuits, e.g. for writing into memory · CPC title

• G11C17/16

  using electrically-fusible links · CPC title

• G11C29/44

  Indication or identification of errors, e.g. for repair · CPC title