Non-volatile memory storage for multi-channel memory system

Patent metadata

Field	Value
Publication number	US-9996284-B2
Application number	US-201615255894-A
Country	US
Kind code	B2
Filing date	Sep 2, 2016
Priority date	Jun 11, 2013
Publication date	Jun 12, 2018
Grant date	Jun 12, 2018

Abstract

A memory system that has a multi-channel volatile memory subsystem is coupled to a non-volatile memory subsystem to provide independent, configurable backup of data. The volatile memory subsystem has one or more main memory modules that use a form of volatile memory such as DRAM memory, for which the NV subsystem provides selective persistent backup. The main memory modules are dual in-line memory modules or DIMMs using DDR SDRAM memory devices. The non-volatile memory subsystem (NV backup) includes an NV controller and non-volatile memory NVM. The NV backup can also include a memory cache to aid with handling and storage of data. In certain embodiments, the NV controller and the non-volatile memory are coupled to the one or more DIMM channels of the main memory via associated signal lines. Such signal lines can be, for example, traces on a motherboard, and may include one or more signal buses for conveying data, address, and/or control signals. The NV controller and the non-volatile memory can be mounted on the motherboard.

First claim

What is claimed is:

1. A hybrid memory system for connection to a host system, the hybrid memory system comprising:
a) a volatile memory subsystem including:
i. one or more volatile memory modules, and
ii. a volatile memory channel associated with each volatile memory module, each volatile memory channel including a set of data lines through which data is deliverable to and from the associated volatile memory module, and a set of address and control lines through which address and control signals are deliverable to and from the associated volatile memory module; and

b) a nonvolatile memory subsystem including:
i. one or more nonvolatile memory controllers, and
ii. at least one nonvolatile memory module associated with one of the one or more nonvolatile memory controllers,
wherein a first nonvolatile memory controller of the one or more nonvolatile memory controllers is operable to monitor a volatile memory channel of the volatile memory subsystem to detect a memory access operation by the host system, and to capture a copy of data associated with the detected memory access operation.

2. The hybrid memory system of claim 1 , wherein the first nonvolatile memory controller is operable to store the captured copy of data in a nonvolatile memory module.

3. The hybrid memory system of claim 1 , wherein the nonvolatile memory subsystem further includes a cache, and
wherein the first nonvolatile memory controller is operable to store the captured copy of data in the cache.

4. The hybrid memory system of claim 3 , wherein the cache comprises volatile memory.

5. The hybrid memory system of claim 1 , wherein the memory access operation comprises a data write operation performed by the memory controller of the host system to at least one of the one or more volatile memory modules.

6. The hybrid memory system of claim 1 , wherein capturing a copy of data associated with the detected memory access operation is performed in response to a trigger signal.

7. The hybrid memory system of claim 6 , wherein the trigger signal is responsive to one or more of a power interruption, a power failure, a power reduction, a system hang-up, a request by the host system, a host system voltage dropping below a threshold voltage, a host system voltage exceeding a threshold voltage, the host system voltage being below a first threshold voltage and above a second threshold voltage, and a reboot condition.

8. A hybrid memory system comprising:
a volatile memory subsystem including one or more volatile memory modules; and
a nonvolatile memory subsystem including one or more nonvolatile memory controllers and one or more nonvolatile memory modules each associated with one of the one or more nonvolatile memory controllers,
wherein a first nonvolatile memory controller of the one or more nonvolatile memory controllers is operable to snoop one or more of data, address or control signals communicated to or from the volatile memory subsystem, and to generate corresponding one or more of data, address or control signals and deliver same to an associated nonvolatile memory module.

9. The hybrid memory system of claim 8 , wherein the first nonvolatile memory controller is operable to detect a memory access operation to the volatile memory subsystem, and to capture a copy of data associated with the detected memory access operation and store the captured copy of data in a nonvolatile memory module.

10. The hybrid memory system of claim 8 , wherein the nonvolatile memory subsystem further includes a cache, and
wherein the first nonvolatile memory controller is operable to detect a memory access operation to the volatile memory subsystem, and to capture a copy of data associated with the detected memory access operation and store the captured copy of data in the cache.

11. The hybrid memory system of claim 10 , wherein the cache comprises volatile memory.

12. The hybrid memory system of claim 9 , wherein the memory access operation comprises a data write operation to at least one of the one or more volatile memory modules.

13. The hybrid memory system of claim 9 , wherein capturing a copy of data associated with the detected memory access operation is performed in response to a trigger signal.

14. The hybrid memory system of claim 13 , wherein the trigger signal is responsive to one or more of a power interruption, a power failure, a power reduction, a system hang-up, a request by the host system, a host system voltage dropping below a threshold voltage, a host system voltage exceeding a threshold voltage, the host system voltage being below a first threshold voltage and above a second threshold voltage, and a reboot condition.

Assignees

• Netlist Inc

Inventors

• Lee Hyun

Classifications

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G06F3/0685

  Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays · CPC title

• G06F3/0653

  Monitoring storage devices or systems · CPC title

• G06F12/0815

  Cache consistency protocols · CPC title

• G06F3/0619 Primary

  in relation to data integrity, e.g. data losses, bit errors · CPC title