Vertical field effect transistor with abrupt extensions at a bottom source/drain structure

Patent metadata

Field	Value
Publication number	US-9991382-B1
Application number	US-201715808178-A
Country	US
Kind code	B1
Filing date	Nov 9, 2017
Priority date	Apr 20, 2017
Publication date	Jun 5, 2018
Grant date	Jun 5, 2018

Abstract

A semiconductor structure is provided that includes a vertical transport field effect transistor located on sidewall surfaces of a semiconductor fin. The semiconductor structure further includes an abrupt junction that is located between a bottom source/drain extension region and a sidewall surface of a lower portion of the semiconductor fin. The bottom source/drain extension region is present in a gap that is located adjacent the lower portion of the semiconductor fin and atop a mesa portion of a base semiconductor substrate.

First claim

What is claimed is:

1. A method of forming a semiconductor structure, the method comprising:
providing at least one semiconductor fin containing a hard mask cap and extending upward from a semiconductor substrate portion, wherein a dielectric layer is present on physically exposed surfaces of the semiconductor substrate portion;
forming a dielectric spacer along sidewall surfaces of the at least one semiconductor fin and the hard mask cap and on a portion of the topmost surface of the dielectric layer;
recessing the semiconductor substrate portion utilizing the dielectric spacer and the hard mask cap as an etch mask to provide a base semiconductor substrate containing at least one mesa portion, wherein during the recessing, physically exposed portions of the dielectric layer which are located beneath the dielectric spacer are removed;
removing the dielectric layer that remains beneath the dielectric spacer to provide a gap positioned between the dielectric spacer and the at least one mesa portion of the base semiconductor substrate and to physically expose the sidewall surfaces of a lower portion of the semiconductor fin;
forming a bottom source/drain structure including a bottom source/drain extension, wherein the bottom source/drain extension region fills the gap and contacts the physically exposed sidewall surfaces of the lower portion of the at least one semiconductor fin;
removing the dielectric spacer from sidewall surfaces of the at least one semiconductor fin;
forming a vertical gate structure comprising a bottom spacer on the physically exposed surfaces of the bottom source/drain structure and the bottom source/drain extension, a gate structure along a portion of the physically exposed sidewall surfaces of the at least one semiconductor fin and atop the bottom spacer, and a top spacer above the gate structure and contacting the sidewall surfaces of an upper portion of the at least semiconductor fin;
removing the hard mask cap; and
forming a top source/drain structure from a physically exposed topmost surface of the at least one semiconductor fin.

2. The method of claim 1 , wherein the at least one semiconductor fin is present on the at least one mesa portion.

3. The method of claim 2 , wherein the at least one mesa portion has a width that is greater than a width of the at least one semiconductor fin.

4. The method of claim 1 , wherein the gate structure comprises a gate dielectric and a gate conductor, wherein a vertical portion of the gate dielectric is in direct physical contact with the sidewall surfaces of the semiconductor fin.

5. The method of claim 4 , further comprising a workfunction metal positioned between the gate dielectric and the gate conductor.

6. The method of claim 1 , wherein the base semiconductor substrate, the mesa portion and the semiconductor fin are of uniform construction and are composed of a same semiconductor material.

7. The method of claim 1 , wherein the dielectric layer has a topmost surface is vertically offset and is located beneath the topmost surface of the at least one semiconductor fin.

8. The method of claim 7 , wherein the dielectric layer is formed by depositing a dielectric structure and then recessing the dielectric structure.

9. The method of claim 1 , wherein the forming the bottom source/drain structure and the bottom source/drain extension comprises epitaxial deposition of a doped semiconductor material.

10. The method of claim 1 , wherein the forming the top source/drain structure comprises epitaxial deposition of a doped semiconductor, and wherein the top source/drain structure has a faceted surfaces.

Assignees

• IBM

Inventors

• Mochizuki Shogo
• Reznicek Alexander

Classifications

• H01L29/7827 Primary

  Electricity · mapped topic

• H01L29/0847

  Electricity · mapped topic

• H01L29/66666

  Electricity · mapped topic

• H01L29/6653

  Electricity · mapped topic

• H10D64/667

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671) · CPC title