Structure for reduced source and drain contact to gate stack capacitance

Patent metadata

Field	Value
Publication number	US-9601570-B1
Application number	US-201615224613-A
Country	US
Kind code	B1
Filing date	Jul 31, 2016
Priority date	Dec 17, 2015
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

A structure of a semiconductor device is described. A device structure including a gate structure, a source region and a drain region is disposed on a first surface of a substrate. Contact holes are etched through the source and drain regions and through a first portion of the substrate. The contact holes are filled with a conductive material to produce contact studs coupled to the source and drain regions. A second portion of the substrate is removed. A surface of the contact studs is exposed through a second surface of the substrate opposite to the gate structure for connection to a wiring layer disposed over the second surface of the substrate.

First claim

Having described our invention, what we now claim is as follows:

1. A semiconductor device comprising:
a transistor including a gate structure, a source region and a drain region disposed on a first surface of a substrate;
a wiring layer of conductive material disposed over a second surface of the substrate, the second surface of the substrate opposite to the first surface of the substrate;
a set of contact studs electrically coupling the source region and the drain region through the substrate to respective portions of the wiring layer; and
a gate contact stud electrically coupling the gate structure through the substrate to a respective portion of the wiring layer disposed over the second surface of the substrate.

2. The device as recited in claim 1 , wherein the device is a planar MOSFET device.

3. The device as recited in claim 1 , wherein the device is a FinFET device.

4. The device as recited in claim 1 , wherein the device is a Nanosheet device.

5. The device as recited in claim 1 , wherein the set of contact studs are composed of tungsten.

6. The device as recited in claim 1 , wherein a layer of dielectric material is disposed between the second surface of the substrate and the wiring layer.

7. The device as recited in claim 1 , wherein the wiring layer is composed of a metal selected from the group consisting of Cu, W, Al and Cu alloy.

8. The device as recited in claim 1 , further comprising a protective insulator layer over the device structure disposed over the first surface of the substrate.

9. The device as recited in claim 1 , wherein the set of contact studs are composed of a material selected from the group of Ti, Mo, Pt and Co.

10. The device as recited in claim 1 , further comprising a set of contact metallurgy disposed between and in physical contact with the set of contact studs and the wiring layer, wherein an area of the wiring layer is larger than an area of the contact metallurgy.

11. The device as recited in claim 1 , the gate contact stud is located on a gate stripe to distance the gate contact stud from the source and drain contact studs to reduce capacitive coupling.

12. The device as recited in claim 4 , further comprising a set of stacked channels between source and drain regions disposed over the first surface of the substrate.

Assignees

• IBM

Inventors

• Radens Carl J
• Williams Richard Q

Classifications

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W20/0249

  wherein the through-semiconductor via protrudes from backsides of the chips, wafers or substrates during the manufacture · CPC title

• H10W20/481

  on the rear surfaces of the wafers or substrates · CPC title

• H10W20/218

  in silicon-on-insulator [SOI] wafers · CPC title

• H10P72/7422

  used to protect an active side of a device or wafer · CPC title