Array substrate manufactured by reduced times of patterning processes manufacturing method thereof and display apparatus

Patent metadata

Field	Value
Publication number	US-9991295-B2
Application number	US-201414772677-A
Country	US
Kind code	B2
Filing date	Nov 21, 2014
Priority date	Aug 15, 2014
Publication date	Jun 5, 2018
Grant date	Jun 5, 2018

Abstract

An array substrate, a manufacturing method thereof and a display apparatus are provided. The array substrate includes thin-film transistors (TFTs) and conductive electrodes; the TFT includes a gate electrode, a source electrode, a drain electrode and an active layer; the source electrode and the drain electrode are arranged in the same layer and at two ends of the active layer and at least directly partially contact the upper surface or the lower surface of the active layer; and the conductive electrode is directly disposed on the electrode. With improved layer structures of the array substrate, a plurality of layer structures is formed in one patterning process by stepped photoresist process, so as to reduce the frequency of patterning processes, better ensure the compactness of the array substrate, and guarantee good contact between the layer structures in the array substrate.

First claim

What is claimed is:

1. A method for manufacturing an array substrate, comprising:
forming a thin film transistor (TFT) and a conductive electrode, in which forming of the TFT includes forming a gate electrode, a source electrode, a drain electrode and an active layer, wherein
a pattern comprising the source electrode, the drain electrode and the conductive electrode is formed by a same one patterning process;
the source electrode and the drain electrode are directly formed at two ends of the active layer, respectively, and the source electrode and the drain electrode directly contact at least a part of an upper surface or a lower surface of the active layer;
the conductive electrode is directly disposed on the drain electrode, a portion, overlapping the drain electrode, of the conductive electrode entirely directly contacts the drain electrode, and the portion, overlapping the drain electrode, of the conductive electrode is outside of a positon where the drain electrode overlaps the active layer.

2. The method according to claim 1 , wherein forming of the pattern comprising the source electrode, the drain electrode and the conductive electrode includes:
forming a source/drain metal film, a conductive film and a photoresist sequentially;
performing exposure and development on the photoresist by a two-tone mask process, in which in a mask adopted by the two-tone mask process, a region configured for forming the source electrode and the drain electrode and not to be covered by the conductive electrode is a partially transmissive region, a region configured for forming the conductive electrode correspondingly is a light-tight region, and a region formed outside of the above regions is a totally transmissive region;
removing the conductive film and the source/drain metal film corresponding to the totally transmissive region by an etching process, to form a pattern comprising the source electrode and the drain electrode; and
removing the photoresist corresponding to the partially transmissive region by an ashing process, removing the conductive film not protected by the photoresist by an etching process, to form a pattern comprising the conductive electrode.

3. The method according to claim 2 , wherein the source/drain metal film is a single-layer structure formed by any one selected from the group consisting of Mo, MoNb, Al, AlNd, Ti and Cu, or is a laminated structure obtained with sub-layers of Mo/Al/Mo or Ti/Al/Ti.

4. The method according to claim 3 , wherein
where the source/drain metal film is a laminated structure obtained with sub-layers of Mo/Al/Mo, a wet etching process is adopted for etching;
where the source/drain metal film is a laminated structure obtained with sub-layers of Ti/Al/Ti, an inductively coupled plasma (ICP) method is adopted for etching.

5. The method according to claim 2 , wherein
the conductive film is a transparent metal oxide conductive film, the metal oxide includes any one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), zinc tin oxide (ZTO) and aluminum zinc oxide (AZO); and has a thickness ranged from 20 to 100 nm; or,
the conductive film is a film of laminated layers obtained with sub-layers of ITO/Ag/ITO or IZO/Ag with a thickness of a ITO film being ranged from 10 to 50 nm and a thickness of the Ag film being ranged from 20 to 100 nm.

6. The method according to claim 5 , wherein the conductive film is etched by a wet etching process.

7. The method according to claim 1 , further comprising:
forming a gate insulating layer between the source and drain electrodes and the gate electrodes, in which:
the gate electrode is formed on the gate insulating layer; a projection of the gate electrode at least partially overlaps with a projection of the active layer; and a projection of the source electrode and the drain electrode at least partially overlaps the projection of the gate electrode; or,
the gate insulating layer is formed on the gate electrode, the active layer is formed on the gate insulating layer; a projection of the gate electrode at least partially overlaps a projection of the active layer; and a projection of the source electrode and the drain electrode at least partially overlaps the projection of the gate electrode.

8. The method according to claim 7 , further comprising:
forming a passivation layer, in which the conductive electrode is formed on an end of the drain electrode away from the active layer, the passivation layer at least partially covers the conductive electrode and the drain electrode and completely covers a region corresponding to the source electrode and the active layer;
where the gate insulating layer is disposed on the source electrode and the drain electrode, a region that corresponds to the passivation layer and the gate insulating layer and is not covered by the conductive electrode forms a pixel opening; or, where the gate insulating layer is disposed beneath the source electrode and the drain electrode, a region that corresponds to the passivation layer and is not covered by the conductive electrode forms a pixel opening.

9. The method according to claim 1 , further comprising:
forming a pattern of a storage capacitor, in which
the active layer and one plate of the storage capacitor are formed by a same one patterning process.

10. The method according to claim 9 , wherein forming of the active layer and the one plate in the storage capacitor includes:
forming a polysilicon film;
forming photoresist, and performing exposure and development on the photoresist by a two-tone mask process, in which in a mask adopted by the two-tone mask process, a region configured for forming the one plate in the storage capacitor is a partially transmissive region, a region configured for forming the active layer is a light-tight region, and a region formed outside of the above regions is a totally transmissive region;
removing the polysilicon film corresponding to the totally transmissive region by an etching process, to form a pattern comprising the active layer and the one plate in the storage capacitor; and
removing the photoresist corresponding to the partially transmissive region by an ashing process, performing ion doping on the one plate in the storage capacitor, to form the active layer and the one plate in the storage capacitor.

11. The method according to claim 10 , wherein ions for the ion doping of the one plate in the storage capacitor are PH 3 /H 2 or B 2 H 6 /H 2 ; an ion implantation dosage is 10 14 ions/cm 2 -10 16 ions/cm 2 ; and an implantation energy is 10 KeV-100 KeV.

Assignees

• Boe Technology Group Co Ltd

Inventors

• Long Chunping
• Wang Zuqiang

Classifications

• H10P70/10

  Cleaning before device manufacture, i.e. Begin-Of-Line process · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/6336

  in the presence of a plasma [PECVD] · CPC title

• H01L21/02043

  Electricity · mapped topic