Semiconductor device

Patent metadata

Field	Value
Publication number	US-9991276-B2
Application number	US-201615070785-A
Country	US
Kind code	B2
Filing date	Mar 15, 2016
Priority date	Sep 11, 2015
Publication date	Jun 5, 2018
Grant date	Jun 5, 2018

Abstract

According to one embodiment, a semiconductor device includes a substrate; a first structure; a second structure; a step; an insulating layer; a first pillar; a second pillar; a first contact portion; and a second contact. The first structure includes a first electrode layer and a first insulator. The first structure has a first terrace on a surface of the first insulator. The second structure includes a second electrode layer and a second insulator. The second structure has a second terrace on a surface of the second insulator. The second contact portion is electrically connected to the second electrode layer via the second terrace. The first contact portion is located between the step and the first pillar. The step is located between the first contact portion and the second pillar.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate;
a first structure provided on the substrate, the first structure including a first electrode layer and a first insulator, the first structure having a first terrace on a surface of the first insulator;
a second structure provided on the first structure except a part on the first terrace, the second structure including a second electrode layer and a second insulator, the second structure having a second terrace on a surface of the second insulator;
a third structure provided on the second structure except a part on the second terrace, the third structure including a third electrode layer and a third insulator, the third structure having a third terrace on a surface of the third insulator;
a first step provided between the first terrace and the second terrace;
a second step provided between the second terrace and the third terrace;
an insulating layer provided on the first terrace, the second terrace, and the third terrace;
a first pillar provided in the insulating layer, the first structure, and the second structure, the first pillar reaching the substrate via the first terrace, the second terrace, and the first step;
a second pillar provided in the insulating layer, the first structure, the second structure, and the third structure, the second pillar reaching the substrate via the second terrace, the third terrace, and the second step;
a first contact portion provided in the insulating layer and the first insulator, the first contact portion electrically connected to the first electrode layer via the first terrace;
a second contact portion provided in the insulating layer and the second insulator, the second contact portion electrically connected to the second electrode layer via the second terrace;
a third contact portion provided in the insulating layer and the third insulator, the third contact portion electrically connected to the third electrode layer via the third terrace;
a third pillar provided in the insulating layer, the first structure, and the second structure, the third pillar reaching the substrate via the first terrace, the second terrace, and the first step; and
a fourth pillar provided in the insulating layer, the first structure, the second structure, and the third structure, the fourth pillar reaching the substrate via the second terrace, the third terrace, and the second step.

2. The device according to claim 1 , further comprising:
a first row including the first pillar and the second pillar; and
a second row including the third pillar and the fourth pillar, wherein
the first row and the second row extend along a direction in the first terrace, the second terrace, and the third terrace arranged.

3. The device according to claim 2 , wherein the first contact portion, the second contact portion, and the third contact portion are located between the first row and the second row.

4. The device according to claim 1 , wherein the first pillar, the second pillar, the third pillar, and the fourth pillar are arranged in a rectangular pattern in a plan view.

5. The device according to claim 1 , wherein the first pillar, the second pillar, the third pillar, and the fourth pillar are arranged in a parallelogram pattern in a plan view.

6. A semiconductor device comprising:
a substrate;
a first structure provided on the substrate, the first structure including a first electrode layer and a first insulator, the first structure having a first terrace on a surface of the first insulator;
a second structure provided on the first structure except a part on the first terrace, the second structure including a second electrode layer and a second insulator, the second structure having a second terrace on a surface of the second insulator;
a third structure provided on the second structure except a part on the second terrace, the third structure including a third electrode layer and a third insulator, the third structure having a third terrace on a surface of the third insulator;
a first step provided between the first terrace and the second terrace;
a second step provided between the second terrace and the third terrace;
an insulating layer provided on the first terrace, the second terrace, and the third terrace;
a first pillar provided in the insulating layer, the first structure, and the second structure, the first pillar reaching the substrate via the first terrace, the second terrace, and the first step;
a second pillar provided in the insulating laver, the first structure, the second structure, and the third structure, the second pillar reaching the substrate via the second terrace, the third terrace, and the second step;
a first contact portion provided in the insulating layer and the first insulator, the first contact portion electrically connected to the first electrode layer via the first terrace;
a second contact portion provided in the insulating layer and the second insulator, the second contact portion electrically connected to the second electrode layer via the second terrace; and
a third contact portion provided in the insulating layer and the third insulator, the third contact portion electrically connected to the third electrode layer via the third terrace,
wherein the first contact portion and the second contact portion have elliptic shapes when viewed from above.

7. A semiconductor device comprising:
a substrate;
a first structure provided on the substrate, the first structure including a first electrode layer and a first insulator, the first structure having a first terrace on a surface of the first insulator;
a second structure provided on the first structure except a part on the first terrace, the second structure including a second electrode layer and a second insulator, the second structure haying a second terrace on a surface of the second insulator;
a third structure provided on the second structure except a part on the second terrace, the third structure including a third electrode layer and a third insulator, the third structure having a third terrace on a surface of the third insulator;
a first step provided between the first terrace and the second terrace;
a second step provided between the second terrace and the third terrace;
an insulating layer provided on the first terrace, the second terrace, and the third terrace;
a first pillar provided in the insulating layer, the first structure, and the second structure, the first pillar reaching the substrate via the first terrace, the second terrace, and the first step;
a second pillar provided in the insulating layer, the first structure, the second structure, and the third structure, the second pillar reaching the substrate via the second terrace, the third terrace, and the second step;
a first contact portion provided in the insulating layer and the first insulator, the first contact portion electrically connected to the first electrode layer via the first terrace;
a second contact portion provided in the insulating layer and the second insulator, the second contact portion electrically connected to the second electrode layer via the second terrace;
a third contact portion provided in the insulating layer and the third insulator, the third contact portion electrically connected to the third electrode layer via the third terrace;
a hole provided in the first structure, the second structure, and the third structure, the hole reaching the substrate;
a first memory cell provided in the hole;
a second memory cell provided in the hole, the second memory cell electrically connected to the first memory cell; and
a third memory cell provided in the hole, the third memory cell electrically connected to the second memory cell.

8. The device according to claim 7 ,

Assignees

• Toshiba Memory Corp

Inventors

• Sonehara Takeshi
• Kito Masaru

Classifications

• H01L27/11582 Primary

  Electricity · mapped topic

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/20 Primary

  characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels · CPC title

• H10B43/50

  characterised by the boundary region between the core and peripheral circuit regions · CPC title

• H10B43/10 Primary

  characterised by the top-view layout · CPC title