Packaging with interposer frame

Patent metadata

Field	Value
Publication number	US-9991190-B2
Application number	US-201213475674-A
Country	US
Kind code	B2
Filing date	May 18, 2012
Priority date	May 18, 2012
Publication date	Jun 5, 2018
Grant date	Jun 5, 2018

Abstract

The mechanisms of using an interposer frame to package a semiconductor die enables fan-out structures and reduces form factor for the packaged semiconductor die. The mechanisms involve using a molding compound to attach the semiconductor die to the interposer frame and forming a redistribution layer on one or both sides of the semiconductor die. The redistribution layer(s) in the package enables fan-out connections and formation of external connection structures. Conductive columns in the interposer frame assist in thermal management.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a substrate including a passivation layer and a first redistribution layer embedded in the passivation layer, wherein a bottom surface of the first redistribution layer is coplanar with a bottom surface of the passivation layer;
an interposer frame directly contacting the substrate, wherein the interposer frame including a first set of a plurality of conductive columns and a second set of the plurality of conductive columns separated from the first set of the plurality of conductive columns by an interval;
a semiconductor die in the interval and directly contacting the substrate;
a second redistribution layer directly contacting a top surface of the semiconductor die and a top surface of the interposer frame; and
a bump on the bottom surface of the first redistribution layer.

2. The semiconductor package of claim 1 , wherein at least one conductive column of the first set of conductive columns comprises a copper-containing via and a solder element.

3. The semiconductor package of claim 1 , further comprising a molding compound between the semiconductor die and the interposer frame.

4. The semiconductor package of claim 1 , wherein each conductive column of the first set of conductive columns are isolated from each other by a molding compound.

5. The semiconductor package of claim 1 , wherein at least one conductive column of the first set of conductive columns comprises:
a first portion having a curved surface; and
a second portion adjoining the first portion, wherein the second portion has a planar surface.

6. The semiconductor package of claim 1 , wherein the interposer frame comprises a molding compound, and at least one conductive column of the first set of conductive columns protrudes from the molding compound.

7. A semiconductor package, comprising:
a passivation layer;
a first redistribution layer embedded in the passivation layer, wherein a bottom surface of the first redistribution layer is coplanar with a bottom surface of the passivation layer;
an interposer frame directly contacting the passivation layer, wherein the interposer frame includes a first set of conductive columns and a second set of conductive columns separated from the first set of conductive columns by an interval;
a semiconductor die in the interval; and
a second redistribution layer directly contacting a top surface of the semiconductor die and a top surface of the interposer frame.

8. The semiconductor package of claim 7 , wherein at least one conductive column of the first set of conductive columns comprises:
a copper-containing via; and
at least a portion of a solder ball.

9. The semiconductor package of claim 8 , wherein the solder ball comprises a curved surface adjoining a planar surface of the copper-containing via.

10. The semiconductor package of claim 7 , further comprising a bump on the bottom surface of the first redistribution layer.

11. The semiconductor package of claim 7 , further comprising a first molding compound between the interposer frame and the semiconductor die.

12. The semiconductor package of claim 11 , wherein the interposer frame comprises a second molding compound, and the second molding compound is different from the first molding compound.

13. The semiconductor package of claim 12 , wherein at least one conductive column of the first set of conductive columns protrudes from the second molding compound.

14. The semiconductor package of claim 7 , wherein the interposer frame is spaced from the semiconductor die in a direction parallel to the bottom surface of the passivation layer.

15. A semiconductor package, comprising:
a passivation layer;
a first redistribution layer embedded in the passivation layer, wherein a bottom surface of the first redistribution layer is coplanar with a bottom surface of the passivation layer;
an interposer frame directly contacting the passivation layer, wherein the interposer frame including a first set of conductive columns and a second set of conductive columns separated from the first set of conductive columns with by an interval;
a semiconductor die in the interval;
a second redistribution layer directly contacting a top surface of the semiconductor die and a top surface of the interposer frame; and
a bump on the bottom surface of the first redistribution layer.

16. The semiconductor package of claim 15 , wherein at least one conductive column of the first set of conductive columns comprises a copper-containing via and a solder element.

17. The semiconductor package of claim 15 , wherein at least one conductive column of the first set of conductive columns comprises a copper-containing via, and the copper-containing via comprises a middle section wider than an end section.

18. The semiconductor package of claim 15 , further comprising a molding compound between the interposer frame and the semiconductor die.

19. The semiconductor package of claim 15 , wherein the interposer frame comprises a first molding compound, and at least one conductive column of the first set of conductive columns protrudes from the first molding compound.

20. The semiconductor package of claim 19 , further comprising a second molding compound different from the first molding compound, wherein the second molding compound is between the first molding compound and the semiconductor die, and the second molding compound directly contacts the at least one conductive column.

Assignees

• Huang hui min
• Hu Yen Chang
• Lin Chih Wei
• Cheng Ming Da
• Liu Chung Shi
• Chen Chen Shien
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Huang Hui-Min
• Hu Yen-Chang
• Lin Chih-Wei
• Cheng Ming-Da
• Liu Chung-Shi
• Chen Chen-Shien

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title