Chip packaging structure of a plurality of assemblies

Patent metadata

Field	Value
Publication number	US-9136207-B2
Application number	US-201314077376-A
Country	US
Kind code	B2
Filing date	Nov 12, 2013
Priority date	Dec 11, 2012
Publication date	Sep 15, 2015
Grant date	Sep 15, 2015

Abstract

Disclosed herein are chip packaging structures for packaging multiple assemblies therein. In one embodiment, a chip packaging structure can include: (i) a first assembly located at a bottom layer of the chip packaging structure; (ii) at least one second assembly located above the first assembly, where the second assembly is electrically connected to the first assembly by a plurality of first protruding structures located under the second assembly; (iii) at least one third assembly located above the second assembly, where the third assembly is electrically connected to the first assembly by a plurality of second protruding structures located outside of the second assembly; and (iv) where a first portion of the third assembly and the plurality of second protruding structures form a bent structure substantially perpendicular to a second portion of the third assembly.

First claim

What is claimed is:

1. A chip packaging structure, comprising:
a) a first assembly;
b) at least one second assembly located above said first assembly, wherein said at least one second assembly is electrically connected to said first assembly by a plurality of first protruding structures located under periphery and internal regions of said at least one second assembly, wherein said at least one second assembly comprises at least one power transistor;
c) at least one third assem…

Assignees

• Silergy Semiconductor Technology Hangzhou Ltd

Inventors

• Tan Xiaochun

Classifications

• H10W90/732

  Electricity · mapped topic

• H10W72/5363

  Electricity · mapped topic

• H10W72/884

  Electricity · mapped topic

• H10W72/877

  Electricity · mapped topic

• H10W72/536

  Electricity · mapped topic