Method of fabricating integrated circuit device by using slurry composition

Patent metadata

Field	Value
Publication number	US-9991127-B2
Application number	US-201615286976-A
Country	US
Kind code	B2
Filing date	Oct 6, 2016
Priority date	Jan 15, 2016
Publication date	Jun 5, 2018
Grant date	Jun 5, 2018

Abstract

A method of fabricating an integrated circuit device may include forming a polishing stop layer and a semiconductor layer on a substrate, and selectively polishing the semiconductor layer from a surface which simultaneously exposes the polishing stop layer and the semiconductor layer, by using a slurry composition including a compound composition and polishing particles. The compound composition may include a sulfonate compound and a terminal amine group-including compound.

First claim

What is claimed is:

1. A method of fabricating an integrated circuit device, the method comprising:
forming a polishing stop layer and a semiconductor layer on a substrate; and
selectively polishing the semiconductor layer from an upper surface, the upper surface simultaneously exposing an upper surface of the polishing stop layer and an upper surface of the semiconductor layer, based on applying a slurry composition to the upper surface, the slurry composition including a compound composition and polishing particles, the compound composition including a sulfonate compound and a terminal amine group-including compound,
wherein the semiconductor layer includes at least one layer of a Ge-containing layer and a Group III-V compound layer.

2. The method according to claim 1 , wherein each of the sulfonate compound and the terminal amine group-including compound includes a polymer having a molecular weight of 1,000 to 1,000,000.

3. The method according to claim 1 , wherein the sulfonate compound includes a polystyrene sulfonate.

4. The method according to claim 1 , wherein the sulfonate compound includes at least one selected from among C10 to C13 alkylbenzene sulfonates, dodecylbenzene sulfonates, α-olefin sulfonates, ligno sulfonates, trimethylsilyl trifluoromethanesulfonate, guaiazulene sulfonates, diisopropyl naphtalene sulfonates, petroleum sulfonates, and toluene sulfonates.

5. The method according to claim 1 , wherein the terminal amine group-including compound includes an amine polymer or an amide polymer.

6. The method according to claim 1 , wherein the terminal amine group-including compound includes at least one selected from among polyacrylamides, polydimethylacrylamides, poly-N-isopropylamides, polyvinylacetamides, polyoxyethyleneamides, polyarylamines, poly(N-methylvinylamines), poly(N-methyldiarylamines), polyoxypropylenediamines, polyvinylamines, and polyetheramines.

7. The method according to claim 1 , wherein the polishing particles include
a metal oxide, an organic or inorganic material-coated metal oxide, or
a colloidal metal oxide.

8. The method according to claim 1 , wherein,
the polishing stop layer is a silicon nitride layer, and
the semiconductor layer is a SiGe layer.

9. The method according to claim 1 , wherein,
the slurry composition further includes at least one selected from among an oxidant, a free radical supplying agent, an auxiliary oxidant, and a pH regulator, and
the compound composition is present in an amount of 0.01 wt % to 10 wt % in the slurry composition.

10. The method according to claim 9 , wherein,
the free radical supplying agent includes an organic acid, and
the auxiliary oxidant includes a nitrate.

11. A method of fabricating an integrated circuit device, the method comprising:
forming a first semiconductor layer on a first region and a second region of a substrate, such that a first portion of the first semiconductor layer is on the first region and a second portion of the first semiconductor layer is on the second region;
forming a mask pattern on the first portion of the first semiconductor layer, the mask pattern covering the first portion of the first semiconductor layer such that the second portion of the first semiconductor layer is exposed by the mask pattern;
forming a recess space on the second region based on at least partially removing the second portion of the first semiconductor layer exposed by the mask pattern;
filling the recess space with a second semiconductor layer to form a combined layer, the combined layer including at least the mask pattern and the second semiconductor layer, the combined layer including an upper surface, the upper surface of the combined layer including an upper surface of the mask pattern and an exposed upper surface of the second semiconductor layer;
polishing the second semiconductor layer based on applying a slurry composition to the upper surface of the combined layer such that the mask pattern is a polishing stop layer, the slurry composition including a compound composition and polishing particles, the compound composition including a sulfonate compound and a terminal amine group-including compound;
removing the mask pattern; and
forming a plurality of fin-type active regions on each of the first region and the second region by patterning each of the first semiconductor layer and the second semiconductor layer.

12. The method according to claim 11 , wherein,
the first semiconductor layer and the second semiconductor layer include different materials selected from among Group IV materials and Group III-V materials, and
the mask pattern is a silicon nitride layer.

13. The method according to claim 11 , wherein the slurry composition further includes at least one selected from among an oxidant, a free radical supplying agent, an auxiliary oxidant, and a pH regulator.

14. The method according to claim 11 , wherein the slurry composition has a pH of about 3 to about 5.

15. The method according to claim 11 , wherein the compound composition includes a polystyrene sulfonate and a polyacrylamide.

16. A method, comprising:
forming a polishing stop layer and a semiconductor layer on a substrate to form a combined layer, the combined layer including an upper surface, the upper surface of the combined layer including an upper surface of the semiconductor layer and an upper surface of the polishing stop layer; and
selectively polishing the semiconductor layer, based on applying a slurry composition to the upper surface of the combined layer, the slurry composition including a compound composition and polishing particles, the compound composition including a sulfonate compound and a terminal amine group-including compound,
wherein the semiconductor layer includes at least one layer of a Ge-containing layer and a Group III-V compound layer.

17. The method of claim 16 , wherein,
the semiconductor layer includes a protruding portion that protrudes from the polishing stop layer such that the upper surface of the semiconductor layer is elevated above the upper surface of the polishing stop layer; and
selectively polishing the semiconductor layer includes substantially removing the protruding portion of the semiconductor layer based on applying the slurry composition to the upper surface of the combined layer.

18. The method of claim 16 , wherein
selectively polishing the semiconductor layer includes applying the slurry composition to the upper surface of the combined layer such that the upper surface of the semiconductor layer is oxidized by the slurry composition to form a surface oxide layer on the semiconductor layer.

19. The method of claim 16 , wherein:
forming the polishing stop layer and the semiconductor layer on the substrate to form the combined layer includes
forming a first semiconductor layer on the substrate,
forming the polishing stop layer on a first portion of the first semiconductor layer, such that a second portion of the first semiconductor layer is exposed by the polishing stop layer,
removing the second portion of the first semiconductor layer to form a recess in the first semiconductor layer, and
forming a second semiconductor layer in the recess, such that the semiconductor layer is the second semiconductor layer.

20. The method of claim 19 , further comprising:
removing the slurry composition and the polishing stop layer to expose, an upper surface of the first semiconductor layer and an upper surface of the second semiconductor layer; and
removing a portion of the second s

Assignees

• Samsung Electronics Co Ltd
• K C Tech Co Ltd

Inventors

• Park Sang-Hyun
• Lee Jae-Hak
• Choi Bo-Hyeok
• Kim Sang-Kyun
• Hur Won-ki

Classifications

• H10P50/694

  characterised by their behaviour during the process, e.g. soluble masks or redeposited masks · CPC title

• H10P50/692

  characterised by their composition, e.g. multilayer masks or materials · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P52/402 Primary

  of semiconductor materials · CPC title

• H01L21/3081

  Electricity · mapped topic