Memory system

Patent metadata

Field	Value
Publication number	US-9990283-B2
Application number	US-201615291834-A
Country	US
Kind code	B2
Filing date	Oct 12, 2016
Priority date	Oct 16, 2015
Publication date	Jun 5, 2018
Grant date	Jun 5, 2018

Abstract

A memory system includes: a first memory device including a plurality of first memories and a first memory controller suitable for controlling the plurality of first memories to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (OS) and an application to access a data storage memory through the first and second memory devices.

First claim

What is claimed is:

1. A memory system comprising:
a first memory device including a plurality of first memories and a first memory controller suitable for controlling the plurality of first memories to store data;
a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and
a processor suitable for executing an operating system (OS) and an application to access a data storage memory through the first and second memory devices,
wherein the first and second memories are separated from the processor,
wherein the processor accesses the second memory device through the first memory device,
wherein the first memory controller transfers a signal between the processor and the second memory device based on at least one of values of a memory selection field and a handshaking information field included in the signal,
wherein the first memory controller includes a plurality of channel controllers respectively corresponding to the plurality of first memories, and suitable for controlling data communication between the processor and a selected one among the plurality of first memories through processor channels and data communication between two or more selected ones among the plurality of first memories through a memory link different from the processor channels, and
wherein the plurality of channel controllers control the two or more selected first memories to perform the data communication directly with one another of the two or more selected first memories through the memory link in response to memory link commands provided from the processor for the two or more selected first memories.

2. The memory system of claim 1 ,
wherein the plurality of first memories and the second memory have first and second latencies, respectively,
wherein the first and second memory devices maintain information of the first and second latencies, respectively, and
wherein the processor separately communicates with each of the first and second memories according to the information of the first and second latencies provided from the first and second memory devices.

3. The memory system of claim 1 , wherein the value of the memory selection field indicates one of the first and second memory devices as a destination of the signal.

4. The memory system of claim 1 , wherein the value of the memory selection field Indicates two or more among the processor and the first and second memory devices as a source and a destination of the signal.

5. The memory system of claim 1 , wherein the value of the handshaking information field indicates the signal as one of a data request signal from the processor to the second memory, a data ready signal from the second memory to the processor and a session start signal from the processor to the second memory.

6. The memory system of claim 1 , wherein the first memory device is a volatile memory device.

7. The memory system of claim 1 , wherein the second memory device is a non-volatile memory device.

8. The memory system of claim 7 , wherein the non-volatile memory device is a non-volatile random access memory device.

9. The memory system of claim 1 , wherein the memory link commands provided from the processor for the two or more among the plurality of first memories includes:
a memory link read command to one among the plurality of first memories; and
a memory link write command to another one among the plurality of first memories.

10. The memory system of claim 9 , wherein the plurality of channel controllers in response to the memory link read command and the memory link write command provide data read from one among the two or more selected first memories to another one among the two or more selected first memories through the memory link so that the read data from the one is directly written into the another one among the two or more selected first memories.

11. A memory system comprising:
a first memory device including a plurality of first memories and a first memory controller suitable for controlling the plurality of first memories to store data;
a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and
a processor suitable for accessing the first memory, and accessing the second memory through the first memory device,
wherein the first memory controller transfers a signal between the processor and the second memory device based on at least one of values of a memory selection field and a handshaking information field included in the signal,
wherein the first memory controller includes a plurality of channel controllers respectively corresponding to the plurality of first memories, and suitable for controlling data communication between the processor and a selected one among the plurality of first memories through processor channels and data communication between two or more selected ones among the plurality of first memories through a memory link different from the processor channels, and
wherein the plurality of channel controllers control the two or more selected first memories to perform the data communication directly with one another of the two or more selected first memories through the memory link in response to memory link commands provided from the processor for the two or more selected first memories.

12. The memory system of claim 11 ,
wherein the plurality of first memories and the second memory have first and second latencies, respectively,
wherein the first and second memory devices maintain information of the first and second latencies, respectively, and
wherein the processor separately communicates with each of the first and second memories according to the information of the first and second latencies provided from the first and the second memory devices.

13. The memory system of claim 11 , wherein the value of the memory selection field indicates one of the first and second memory devices as a destination of the signal.

14. The memory system of claim 11 , wherein the value of the memory selection field indicates two or more among the processor and the first and second memory devices as a source and a destination of the signal.

15. The memory system of claim 11 , wherein the value of the handshaking information field indicates the signal as one of a data request signal from the processor to the second memory, a data ready signal from the second memory to the processor and a session start signal from the processor to the second memory.

16. The memory system of claim 11 , wherein the first memory device is a volatile memory device.

17. The memory system of claim 11 , wherein the second memory device is a non-volatile memory device.

18. The memory system of claim 17 , wherein the non-volatile memory device is a non-volatile random access memory device.

19. The memory system of claim 11 , wherein the memory link commands provided from the processor for the two or more among the plurality of first memories includes:
a memory link read command to one among the plurality of first memories; and
a memory link write command to another one among the plurality of first memories.

20. The memory system of claim 19 , wherein the plurality of channel controllers in response to the memory link read command and the memory link write command provide data read from one among the two or more selected first memories to another one among the two or more selected first memories through the memory link so that the read data from t

Assignees

• Sk Hynix Inc

Inventors

• Lee Do-Yun
• Kim Min-Chang
• Kim Chang-Hyun
• Lee Yong-Woo
• Lee Jae-Jin
• Jung Hoe-Kwon

Classifications

• G06F12/0638 Primary

  Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module (address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70) · CPC title

• G06F9/00

  Arrangements for program control, e.g. control units (program control for peripheral devices G06F13/10) · CPC title

• G06F2212/205

  Hybrid memory, e.g. using both volatile and non-volatile memory · CPC title

• G06F13/00

  Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units (interface circuits for specific input/output devices G06F3/00 {; multiprogram control therefor  G06F9/46}; multiprocessor systems  G06F15/16 ) · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title