Method and apparatus to shutdown a memory channel

Patent metadata

Field	Value
Publication number	US-9612649-B2
Application number	US-201113997999-A
Country	US
Kind code	B2
Filing date	Dec 22, 2011
Priority date	Dec 22, 2011
Publication date	Apr 4, 2017
Grant date	Apr 4, 2017

Abstract

A method is described that includes deciding to enter a lower power state, and, shutting down a memory channel in a computer system in response where thereafter other memory channels in the computer system remain active so that computer remains operative while the memory channel is shutdown.

First claim

What is claimed is:

1. A method, comprising:
performing the following in response to a desire to enter into a lower performance state:
migrating cache lines stored on a dynamic random access memory (DRAM) memory channel into other DRAM memory channels and active non volatile system memory, said active non volatile system memory being accessible at cache line granularity and from which software program code is able to directly execute out of, where, those of said cache lines associated with more frequently used virtual addresses are migrated into said other DRAM memory channels, and, those of said cache lines associated with less frequently used virtual addresses are migrated into said active non volatile system memory; and,
shutting down said DRAM memory channel.

2. The method of claim 1 wherein said cache lines migrated into active non volatile system memory are migrated into storage space previously reserved in said active non volatile system memory for cache lines that migrate from DRAM storage in response to a DRAM memory channel shutdown operation.

3. The method of claim 2 wherein said method further comprises performing the following in response to a desire to enter into a higher performance state:
re-activating said DRAM memory channel;
migrating those of said cache lines migrated into active non volatile system memory onto said DRAM memory channel.

4. The method of claim 1 further comprising updating virtual to physical address translations for said cache lines.

5. The method of claim 4 wherein said virtual to physical address translations are stored in storage space of said other DRAM memory channels.

6. The method of claim 5 further comprising invalidating any virtual to physical address translations for said cache lines found in a translation look aside buffer.

7. A method, comprising:
tracking usage of virtual addresses of a software program; and,
performing the following in response to a desire to enter into a lower performance state:
reading cache lines from dynamic random access memory (DRAM) memory channels associated with lesser used virtual addresses of said software program;
writing said cache lines into active non volatile system memory, said active non volatile system memory being accessible at cache line granularity and from which said software program is able to directly execute out of;
writing cache lines associated with more frequently used virtual addresses of one of said DRAM memory channels into locations of the other remaining one or more DRAM channels, said locations previously storing at least some of said cache lines written into active non volatile system memory; and,
shutting down said one DRAM memory channel.

8. The method of claim 7 wherein said cache lines written into active non volatile system memory are written into storage space of said active non volatile system memory previously reserved for the storage of cache lines migrating from DRAM storage space.

9. The method of claim 8 further comprising performing the following in response to a desire to enter into a higher performance state:
re-activating said one DRAM memory channel;
migrating said cache lines written into active non volatile system memory onto said DRAM memory channel.

10. The method of claim 7 further comprising updating virtual to physical address translations for said cache lines associated with lesser used virtual addresses and said cache lines associated with more frequently used virtual addresses.

11. The method of claim 10 further comprising invalidating any virtual to physical address translations found in a translation look aside buffer for said cache lines associated with lesser used virtual addresses and said cache lines associated with more frequently used virtual addresses.

12. A machine readable storage medium, and not transitory signal energy, containing program code that when processed by a central processing unit of a computing system causes a method to be performed, said method comprising:
performing the following in response to a desire to enter into a lower performance state:
migrating cache lines stored on a dynamic random access memory (DRAM) memory channel into other DRAM memory channels and active non volatile system memory, said active non volatile system memory being accessible at cache line granularity and from which software program code is able to directly execute out of, where, those of said cache lines associated with more frequently used virtual addresses are migrated into said other DRAM memory channels, and, those of said cache lines associated with less frequently used virtual addresses are migrated into said active non volatile system memory; and,
shutting down said DRAM memory channel.

13. The machine readable storage medium of claim 12 wherein said cache lines migrated into non volatile system memory are migrated into storage space previously reserved in said active non volatile system memory for cache lines that migrate from DRAM storage in response to a DRAM memory channel shutdown operation.

14. The machine readable storage medium of claim 13 wherein said method further comprises performing the following in response to a desire to enter into a higher performance state:
re-activating said DRAM memory channel;
migrating those of said cache lines migrated into active non volatile system memory onto said DRAM memory channel.

15. The machine readable storage medium of claim 12 wherein said method further comprises updating virtual to physical address translations for said cache lines.

16. The machine readable storage medium of claim 15 wherein said virtual to physical address translations are stored in storage space of said other DRAM memory channels.

17. The machine readable storage medium of claim 16 further comprising invalidating any virtual to physical address translations for said cache lines found in a translation look aside buffer.

18. A computer system, comprising:
a plurality of processing cores;
a system memory comprising a plurality of DRAM channels and non volatile memory devices, the non volatile memory devices being accessible at cache line granularity and from which software program code is able to directly execute out of;
a memory controller couple between the plurality of processing cores and the system memory;
a machine readable storage medium containing program code that when processed by at least one of the processing cores causes a method to be performed upon the system memory, said method comprising:
performing the following in response to a desire to enter into a lower performance state:
migrating cache lines stored on a first of the DRAM memory channels into other ones of the DRAM memory channels and one or more of the non volatile memory devices, where, those of said cache lines associated with more frequently used virtual addresses are migrated into said other DRAM memory channels, and, those of said cache lines associated with less frequently used virtual addresses are migrated into said active non volatile system memory; and,
shutting down said first of the DRAM memory channels.

Assignees

• Nachimuthu Murugasamy K
• Kumar Mohan J
• Intel Corp

Inventors

• Nachimuthu Murugasamy K
• Kumar Mohan J

Classifications

• G06F2212/205

  Hybrid memory, e.g. using both volatile and non-volatile memory · CPC title

• G06F3/0647

  Migration mechanisms · CPC title

• G06F2212/1028

  Power efficiency · CPC title

• G06F12/0888

  using selective caching, e.g. bypass · CPC title

• G06F2212/2024

  Rewritable memory not requiring erasing, e.g. resistive or ferroelectric RAM · CPC title