Memory system

Patent metadata

Field	Value
Publication number	US-9990143-B2
Application number	US-201615291902-A
Country	US
Kind code	B2
Filing date	Oct 12, 2016
Priority date	Oct 16, 2015
Publication date	Jun 5, 2018
Grant date	Jun 5, 2018

Abstract

A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (OS) and an application, and accessing data storage memory through the first and second memory devices.

First claim

What is claimed is:

1. A memory system comprising:
a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data;
a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and
a processor suitable for executing an operating system (OS) and an application to access a data storage memory through the first and second memory devices,
wherein the first and second memories are separated from the processor,
wherein the processor accesses the second memory device through the first memory device,
wherein the first memory controller transfers a signal between the processor and the second memory device based on at least one of values of a memory selection field and a handshaking information field included in the signal, and
wherein the memory system includes:
one or more stacked semiconductor chips corresponding to the first and second memory devices;
a plurality of first through-chip vias vertically penetrating the stacked semiconductor chips, and suitable for transferring signals and power supplies; and
a semiconductor substrate including:
a peripheral circuit region electrically coupled to the plurality of first through-chip vias, and suitable for controlling the stacked semiconductor chips based on the signals and power supplies transferred through the plurality of first through-chip vias; and
a conductivity pattern region suitable for transferring the signals and power supplies between an external controller and the peripheral circuit region.

2. The memory system of claim 1 ,
wherein the plurality of first memories and the second memory have first and second latencies, respectively,
wherein the first and second memory devices maintain information of the first and second latencies, respectively, and
wherein the processor separately communicates with each of the first and second memories according to the information of the first and second latencies provided from the plurality of first memories and the second memory.

3. The memory system of claim 1 , wherein the value of the memory selection field indicates one of the first and second memory devices as a destination of the signal.

4. The memory system of claim 1 , wherein the value of the memory selection field indicates two or more among the processor and the first and second memory devices as a source and a destination of the signal.

5. The memory system of claim 1 , wherein the value of the handshaking information field indicates the signal as one of a data request signal from the processor to the second memory, a data ready signal from the second memory to the processor and a session start signal from the processor to the second memory.

6. The memory system of claim 1 , wherein the first memory device is a volatile memory device.

7. The memory system of claim 1 , wherein the second memory device is a non-volatile memory device.

8. The memory system of claim 7 , wherein the second memory device is a non-volatile random access memory device.

9. The memory system of claim 1 , wherein the semiconductor substrate further includes a plurality of external connection terminals electrically coupled to the external controller.

10. The memory system of claim 9 ,
wherein the peripheral circuit region and the conductivity pattern region are formed on an upper side of the semiconductor substrate, and
wherein the plurality of the external connection terminals are formed on a lower side of the semiconductor substrate.

11. The memory system of claim 10 , further comprising a plurality of second through-chip vias suitable for electrically coupling the conductivity pattern region and the plurality of the external connection terminals.

12. The memory system of claim 11 , wherein each of the plurality of first and second through-chip vias is a through-silicon via (TSV).

13. The memory system of claim 1 , wherein the semiconductor substrate is a silicon substrate.

14. The memory system of claim 9 , wherein the conductivity pattern region includes a metal line.

15. The memory system of claim 9 , further comprising one or more bump pads suitable for electrically coupling the plurality of first through-chip vias to the peripheral circuit region.

16. A memory system comprising:
a first memory device including a first memory and first memory controller suitable for controlling the first memory to store data;
a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and
a processor suitable for accessing the first memory, and accessing the second memory through the first memory device,
wherein the first memory controller transfers a signal between the processor and the second memory device based on at least one of values of a memory selection field and a handshaking information field included in the signal, and
wherein the memory system includes:
one or more stacked semiconductor chips corresponding to the first and second memory devices;
a plurality of first through-chip vias vertically penetrating the stacked semiconductor chips, and suitable for transferring signals and power supplies; and
a semiconductor substrate including:
a peripheral circuit region electrically coupled to the plurality of first through-chip vias, and suitable for controlling the stacked semiconductor chips based on the signals and power supplies transferred through the plurality of first through-chip vias; and
a conductivity pattern region suitable for transferring the signals and power supplies between an external controller and the peripheral circuit region.

17. The memory system of claim 16 ,
wherein the plurality of first memories and the second memory have first and second latencies, respectively,
wherein the first and second memory devices maintain information of the first and second latencies, respectively, and
wherein the processor separately communicates with each of the first and second memories according to the information of the first and second latencies provided from the plurality of first memories and the second memory.

18. The memory system of claim 16 , wherein the value of the memory selection field indicates two or more among the processor and the first and second memory devices as a source and destination of the signal.

19. The memory system of claim 16 , wherein the value of the handshaking information field indicates the signal as one of a data request signal from the processor to the second memory, a data ready signal from the second memory to the processor and a session start signal from the processor to the second memory.

20. The memory system of claim 16 ,
wherein the semiconductor substrate further includes a plurality of external connection terminals electrically coupled to the external controller, and
further comprising a plurality of second through-chip vias suitable for electrically coupling the conductivity pattern region and the plurality of the external connection terminals.

Assignees

• Sk Hynix Inc

Inventors

• Lee Do-Yun
• Kim Min-Chang
• Kim Chang-Hyun
• Lee Yong-Woo
• Lee Jae-Jin
• Jung Hoe-Kwon

Classifications

• G06F2212/60

  Details of cache memory · CPC title

• G06F3/0688

  Non-volatile semiconductor memory arrays · CPC title

• G06F3/0622

  in relation to access · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F12/0802

  Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches · CPC title