System and method to detect time-delays in non-periodic signals

Patent metadata

Field	Value
Publication number	US-9989989-B2
Application number	US-201715581014-A
Country	US
Kind code	B2
Filing date	Apr 28, 2017
Priority date	May 5, 2014
Publication date	Jun 5, 2018
Grant date	Jun 5, 2018

Abstract

A system and method for measuring time delays in a non-periodic system can include receiving a first host signal including transitions deviating from a true periodic signal, removing deviations from the true periodic signal to form a second host signal, detecting a phase of the first host signal and the second host signal relative to a common stable clock signal, and comparing the detected phase of the first host signal and the second host signal to produce a signal indicative of the deviation of the first host signal from the true periodic signal.

First claim

What is claimed is:

1. A method for measuring time delays in a non-periodic system, the method comprising:
receiving a first host signal including transitions deviating from a true periodic signal;
removing deviations from the true periodic signal to form a second host signal;
detecting a phase of the first host signal and the second host signal relative to a common stable clock signal;
comparing the detected phase of the first host signal and the second host signal to produce a signal indicative of the deviation of the first host signal from the true periodic signal.

2. The method of claim 1 , further comprising deriving data from the signal indicative of the deviation of the first host signal from the true periodic signal.

3. The method of claim 1 , wherein removing deviations from the true periodic signal to form a second host signal includes removing deviations from the true periodic signal using a stable clock signal.

4. The method of claim 3 , wherein the stable clock signal and the common stable clock signal are the same signal.

5. The method of claim 3 , herein the second host signal has negligible relative timing variations.

6. The method of claim 3 , wherein the stable clock signal has timing stability that is better than the deviations of the first host signal.

7. The method of claim 3 , wherein the first host signal and the stable clock signal include an identical known deviation from the true periodic signal.

8. The method of claim 1 , wherein comparing the detected phase of t first host signal and the second host signal includes adding or subtracting the phase detected first and second host signals.

9. The method of claim 1 , wherein the first host signal is a digital signal.

10. The method of claim 1 , wherein the first host signal is an analog signal.

11. A system for measuring time delays in a non-periodic system, the system comprising:
a processor configured to receive a first host signal including transitions deviating from a true periodic signal and remove deviations from the true periodic signal to form a second host signal;
a first phase detector to detect a phase of the first host signal relative to a common stable clock;
a second phase detector to detect a phase of the second host signal relative to the common stable clock; and
a comparator configured to compare the detected phase of the first host signal and the second host signal to produce a signal indicative of the deviation of the first host signal from the true periodic signal.

12. The system of claim 11 , wherein the processor is configured to derive data from the signal indicative of the deviation of the first host signal from the true periodic signal.

13. The system of claim 11 , wherein the processor is configured to remove deviations from the true periodic signal using a stable clock signal.

14. The system of claim 13 , wherein the stable clock signal and the common stable clock signal are the same signal.

15. The system of claim 13 , wherein the second host signal as negligible relative timing variations.

16. The system of claim 13 , wherein the stable clock signal has timing stability that is better than the deviations of the first host signal.

17. The system of claim 13 , wherein the first host signal and the stable clock signal include an identical known deviation from the true periodic signal.

18. The system of claim 11 , wherein comparing the detected phase of the first host signal and the second host signal includes adding or subtracting the phase detected first and second host signals.

19. The system of claim 11 , wherein the first host signal is a digital signal.

20. The system of claim 11 , wherein the first host signal is an analog signal.

Assignees

• Raytheon Co

Inventors

• Kowalevicz Andrew

Classifications

• H04L7/065

  and superimposed by modulation · CPC title

• G06F1/12 Primary

  Synchronisation of different clock signals {provided by a plurality of clock generators} · CPC title

• H04L7/042

  Detectors therefor, e.g. correlators, state machines (digital correlators in general G06F17/15) · CPC title

• G09C1/00

  Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system (cryptographic typewriters G09C3/00) · CPC title

• H04L43/0864

  Round trip delays · CPC title