System and method to detect time-delays in non-periodic signals

US9698835B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9698835-B2
Application numberUS-201514704929-A
CountryUS
Kind codeB2
Filing dateMay 5, 2015
Priority dateMay 5, 2014
Publication dateJul 4, 2017
Grant dateJul 4, 2017

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  2. Abstract

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  5. First independent claim

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Abstract

Official abstract text for this publication.

A method for carrying data on a live host signal, comprising the steps of: varying timing in a host signal in response to data to be encoded, wherein variations in timing are smaller than a sampling period for detection and capture of the digital signal receiving the live host signal; sensing pulse timing variations in the received live host signal by comparison to a reference signal; and determining information in the sensed timing variations.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for measuring timing variations and/or deviation from ideal waveform transitions in a first host signal, comprising: reconstructing a second host signal using the first host signal with reference to a stable clock signal; simultaneously phase detecting both the first host signal and the second host signal against a common stable clock signal; and comparing the phase detected signals for producing a signal indicating the relative timing variation within the first host signal. 2. The method of claim 1 , further comprising the step of deriving data from the indicated relative timing variation within the first host signal. 3. The method of claim 1 , wherein the stable clock signal and the common clock signal are the same signal. 4. The method of claim 1 , wherein the second host signal reconstructed with reference to the stable clock signal has negligible relative timing variation. 5. The method of claim 1 , wherein the stable clock signal has timing stability that is better than the timing variations of the first host signal. 6. The method of claim 1 , wherein the first host signal and the clock signal include an identical known timing variation. 7. The method of claim 1 , wherein the step of comparing adds or subtracts the phase detected first and second host signals. 8. The method of claim 1 , wherein the first host signal is a digital signal. 9. The method of claim 1 , wherein the first host signal is an analog signal. 10. A system for measuring timing variations and/or deviation from ideal waveform transitions in a first host signal, comprising: a processor adapted to reconstructing a second host signal using the first host signal with reference to a stable clock signal; a pair of phase detectors coupled to simultaneously phase detect both the first host signal and the second host signal against a common stable clock signal; and a comparator coupled for comparing the phase detected signals from the pair of phase detectors for producing a signal indicating the relative timing variation within the first host signal. 11. The system of claim 10 , wherein the processor constructs the second host signal to have negligible relative timing variation. 12. The system of claim 10 , further comprising a stable oscillator or clock for providing the stable clock signal and the common clock signal. 13. The system of claim 12 , wherein the stable clock signal has timing stability that is better than the timing variations of the first host signal. 14. The system of claim 10 , wherein the comparator adds or subtracts the phase detected first and second host signals.

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Classifications

  • H04B1/0475Primary

    with means for limiting noise, interference or distortion (H04B1/0483 takes precedence) · CPC title

  • Detectors therefor, e.g. correlators, state machines (digital correlators in general G06F17/15) · CPC title

  • the keys or algorithms being changed during operation · CPC title

  • Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system (cryptographic typewriters G09C3/00) · CPC title

  • Jitter · CPC title

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What does patent US9698835B2 cover?
A method for carrying data on a live host signal, comprising the steps of: varying timing in a host signal in response to data to be encoded, wherein variations in timing are smaller than a sampling period for detection and capture of the digital signal receiving the live host signal; sensing pulse timing variations in the received live host signal by comparison to a reference signal; and deter…
Who is the assignee on this patent?
Raytheon Co
What technology area does this patent fall under?
Primary CPC classification H04B1/0475. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 04 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).