On-die electric cosmic ray detector

Patent metadata

Field	Value
Publication number	US-9989655-B2
Application number	US-201514829485-A
Country	US
Kind code	B2
Filing date	Aug 18, 2015
Priority date	Nov 20, 2012
Publication date	Jun 5, 2018
Grant date	Jun 5, 2018

Abstract

Described is a chip comprising: a substrate; a logic unit forming an active circuit on the substrate; and a cosmic ray detector embedded in the substrate, the cosmic ray detector to detect a cosmic ray and to generate a signal indicating detection of the cosmic ray, the signal for reducing error in the logic unit.

First claim

I claim:

1. A semiconductor chip, comprising:
a cosmic ray detector comprised of multiple wires that are coupled to a single sense amplifier, an output of the single sense amplifier coupled to a filter, the cosmic ray detector to generate a signal indicating detection of a cosmic ray; and,
a logic unit coupled downstream from the filter to reduce error in a region of the semiconductor chip that received the cosmic ray.

2. The semiconductor chip of claim 1 wherein the multiple wires are disposed over 1000s of square microns.

3. The semiconductor chip of claim 1 wherein the sense amplifier is a differential amplifier.

4. The semiconductor chip of claim 3 wherein the logic unit is to roll-back an executing or executed instruction in response to the signal.

5. The semiconductor chip of claim 3 wherein the logic unit is to generate an interrupt in response to the signal.

6. The semiconductor chip of claim 3 wherein the logic unit is to initiate and determine in response to the signal, whether to address at least one of: soft errors in the semiconductor chip; hard errors in the semiconductor chip; or device aging and variation in the semiconductor chip.

7. The semiconductor chip of claim 1 wherein the logic unit further comprises a counter to count a number of times a region of the semiconductor chip has received cosmic rays.

8. A semiconductor chip,
comprising:
a substrate;
multiple wires that are coupled to a single sense amplifier that is also formed on the substrate, the multiple wires to detect a cosmic ray, a filter coupled to the output of the sense amplifier; and,
a logic unit to reduce error in a region of active circuits of the semiconductor chip on the substrate that received the cosmic ray.

9. The semiconductor chip of claim 8 , wherein the wires are positioned close enough to detect a cloud of charged particles from the cosmic ray.

10. The semiconductor chip of claim 8 , wherein the multiple wires are positioned over 1000s of square microns.

11. A system comprising:
a) a memory unit;
b) a processor, coupled to the memory unit, the processor comprising:
i) a substrate;
ii) an active circuit on the substrate; and,
iii) a cosmic ray detector, the cosmic ray detector comprised of multiple wires that are coupled to a single sense amplifier, a filter coupled to the output of the sense amplifier, the cosmic ray detector to generate a signal indicating detection of acosmic ray;
iv) a logic unit coupled downstream from the filter to reduce error in a region of the active circuit that received the cosmic ray; and,

c) a wireless interface for communicatively coupling the system with another device.

12. The system of claim 11 further comprising a display unit.

13. The system of claim 11 wherein the logic unit is to roll-back an executing or executed instruction according to a level of the sense signal.

14. The system of claim 11 , wherein the multiple wires are positioned close enough to detect a cloud of charged particles from the cosmic ray.

Assignees

• Intel Corp

Inventors

• Hannah Eric C

Classifications

• G01R31/317

  Testing of digital circuits · CPC title

• G01R31/31816 Primary

  Soft error testing; Soft error rate evaluation; Single event testing · CPC title

• G01T1/247 Primary

  Detector read-out circuitry (for processing gain or off-set correction H04N) · CPC title

• G06F11/0793

  Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40) · CPC title