Systems and methods for latch-up detection and mitigation

Patent metadata

Field	Value
Publication number	US-9819258-B1
Application number	US-201615283084-A
Country	US
Kind code	B1
Filing date	Sep 30, 2016
Priority date	Sep 30, 2016
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

Systems and methods for latch-up detection and mitigation. One aspect includes a method implemented in a system divided into a plurality of power blocks, where each power block is powered by a corresponding power rail and includes a voltage droop monitoring circuitry. The method comprises receiving frequency information from the plurality of voltage droop monitoring circuitries; normalizing the received frequency information from each of the plurality of voltage droop monitoring circuitries; creating a matrix of cross-correlation values based on the normalized frequency information between each pair of the plurality of power blocks; determining deviations in the cross-correlation values indicating an occurrence of voltage droop; determining an abnormal variation based on the determined deviations to identify a first power block, out of the plurality of power blocks, experiencing a latch-up event; and resetting power to the first power block without interrupting power to rest of the plurality of power blocks.

First claim

What is claimed is:

1. A system comprising:
a plurality of voltage droop monitoring circuitries, each voltage droop monitoring circuitry corresponding to one of a plurality of power blocks, wherein each power block is powered by a corresponding power rail;
a latch-up detection circuitry communicatively coupled to the plurality of voltage droop monitoring circuitries, the latch-up detection circuitry to:
receive frequency information from the plurality of voltage droop monitoring circuitries; and
determine an abnormal variation based on the received frequency information to identify a first power block, out of the plurality of power blocks, experiencing a latch-up event; and

a voltage regulator circuitry communicatively coupled to the latch-up detection circuitry and each of the corresponding power rails, the voltage regulator circuitry to:
cause a power reset in the first power block without interrupting power to rest of the plurality of power blocks.

2. The system of claim 1 , wherein each of the plurality of voltage droop monitoring circuitries comprises a ring oscillator and a counter.

3. The system of claim 2 , wherein the ring oscillator measures a frequency based on a voltage of the power rail.

4. The system of claim 2 , wherein the ring oscillator measures a frequency based on a current of the power rail.

5. The system of claim 1 , wherein the latch-up detection circuitry further to:
normalize the received frequency information from each of the plurality of voltage droop monitoring circuitries;
create a matrix of cross-correlation values based on the normalized received frequency information between each pair of the plurality of power blocks; and
determine deviations in the cross-correlation values indicating an occurrence of voltage droop.

6. The system of claim 5 , wherein the latch-up detection circuitry further to:
assign a likelihood of latch-up based on the determined deviations in the cross-correlation values.

7. The system of claim 6 , wherein the likelihood of latch-up comprises a plurality of levels.

8. The system of claim 7 , wherein each level of the plurality of levels is associated with one or more mitigation measures.

9. The system of claim 8 , wherein the one of the one or more mitigation measures comprises signaling the voltage regulator circuitry to reset power to the first power block.

10. The system of claim 9 , wherein the one of the one or more mitigation measures comprises reporting the latch-up event to a system administrator.

11. A method implemented in an integrated circuit, the method comprising:
receiving frequency information from a plurality of voltage droop monitoring circuitries, wherein each voltage droop monitoring circuitry corresponds to one of a plurality of power blocks, each power block powered by a respective power rail;
determining an abnormal variation based on the received frequency information to identify a first power block, out of the plurality of power blocks, experiencing a latch-up event; and
resetting power to the first power block without interrupting power to rest of the plurality of power blocks.

12. The method of claim 11 , wherein each of the plurality of voltage droop monitoring circuitries comprises a ring oscillator and a counter.

13. The method of claim 12 , further comprises measuring a frequency of the ring oscillator based on a voltage of the power rail.

14. The method of claim 12 , further comprises measuring a frequency of the ring oscillator based on a current of the power rail.

15. The method of claim 11 , further comprises:
normalizing the received frequency information from each of the plurality of voltage droop monitoring circuitries;
creating a matrix of cross-correlation values based on the normalized frequency information between each pair of the plurality of power blocks; and
determining deviations in the cross-correlation values indicating an occurrence of voltage droop.

16. The method of claim 15 , further comprises:
assigning a likelihood of latch-up based on the determined deviations in the cross-correlation values.

17. The method of claim 16 , wherein the likelihood of latch-up comprises a plurality of levels.

18. The method of claim 17 , wherein each level of the plurality of levels is associated with one or more mitigation measures.

19. The method of claim 11 , further comprises storing a report of the latch-up event in a system log.

20. The method of claim 11 , further comprises reporting the latch-up event to a system administrator.

Assignees

• Intel Corp

Inventors

• Vandam Clark
• Kumar Suriya
• Sindia Suraj
• Ascazubi Ricardo
• Shirota Curtis

Classifications

• H02M1/32 Primary

  Means for protecting converters other than automatic disconnection · CPC title

• H02M1/36

  Means for starting or stopping converters · CPC title

• G01R31/31816 Primary

  Soft error testing; Soft error rate evaluation; Single event testing · CPC title