Device for measuring threshold voltage of a transistor based on constant drain voltage and constant drain source current

Patent metadata

Field	Value
Publication number	US-9989582-B2
Application number	US-201615006038-A
Country	US
Kind code	B2
Filing date	Jan 25, 2016
Priority date	Jul 2, 2015
Publication date	Jun 5, 2018
Grant date	Jun 5, 2018

Abstract

A threshold voltage measuring device may include a metal-oxide-semiconductor (MOS) transistor, a drain voltage clamping circuit configured to control a drain voltage of the MOS transistor wherein the drain voltage having a substantially constant level, and a constant current supply circuit configured to cause a drain-source current to flow through the MOS transistor wherein the drain-source current having a substantially constant magnitude.

First claim

What is claimed is:

1. A threshold voltage measuring device comprising:
a metal-oxide-semiconductor (MOS) transistor;
a drain voltage clamping circuit configured to control a drain voltage of the MOS transistor, the drain voltage having a substantially constant level; and
a constant current supply circuit configured to cause a drain-source current to flow through the MOS transistor, the drain-source current having a substantially constant magnitude.

2. The threshold voltage measuring device of claim 1 , wherein a voltage of a source of the MOS transistor has substantially the same level as that of a back gate of the MOS transistor.

3. The threshold voltage measuring device of claim 2 , wherein the MOS transistor is an NMOS transistor, and
wherein the source and the back gate of the MOS transistor are coupled to a ground.

4. The threshold voltage measuring device of claim 2 , wherein the MOS transistor is a PMOS transistor, and
wherein the source and the back gate of the MOS transistor are coupled to a supply voltage.

5. The threshold voltage measuring device of claim 1 , wherein the drain voltage clamping circuit comprises a first amplifier configured to control a gate voltage of the MOS transistor by amplifying a difference between the drain voltage and a set voltage.

6. The threshold voltage measuring device of claim 5 , wherein the constant current supply circuit comprises:
a reference current source configured to generate a reference current; and
a current replication circuit configured to replicate the reference current and provide a current that causes the drain-source current to flow through the MOS transistor.

7. The threshold voltage measuring device of claim 6 , wherein the current replication circuit comprises:
a regulator configured to regulate a supply voltage according to a feedback voltage and output a rectified voltage;
a first resistor coupled between an output of the regulator and a drain of the MOS transistor;
a second resistor having first and second terminals, the first terminal coupled to the reference current source, a first voltage at the first terminal corresponding to a reference voltage, a second voltage at the second terminal corresponding to the set voltage; and
a second amplifier configured to amplify a difference between the rectified voltage and the reference voltage and provide the feedback voltage to the regulator.

8. The threshold voltage measuring device of claim 6 , wherein the reference current has a magnitude that is substantially equal to that of the drain-source current.

9. A threshold voltage measuring device comprising:
a transistor array comprising a plurality of MOS transistors arranged in a matrix, the matrix being defined by a plurality of rows and a plurality of columns;
a row selector configured to apply a gate voltage to a selected row among the plurality of rows according to a row select signal;
a column selector configured to select a column among the plurality of columns according to a column select signal;
a bias controller configured to apply a bias voltage to unselected rows among the plurality of rows;
a drain voltage clamping circuit configured to provide a drain voltage of a MOS transistor selected by the row select signal and the column select signal, the drain voltage having a substantially constant level; and
a constant current supply circuit configured to cause a drain-source current to flow through the selected MOS transistor, the drain-source current having a substantially constant magnitude.

10. The threshold voltage measuring device of claim 9 , wherein a voltage of a source and a voltage of a back gate of each of the MOS transistors included in the transistor array have substantially the same level.

11. The threshold voltage measuring device of claim 10 , wherein the MOS transistors are NMOS transistors, and
wherein the source and the back gate of each of the NMOS transistors are coupled to a ground.

12. The threshold voltage measuring device of claim 10 , wherein the MOS transistors are PMOS transistors, and
wherein the source and the back gate of each of the PMOS transistors are coupled to a supply voltage.

13. The threshold voltage measuring device of claim 9 , wherein the drain voltage clamping circuit comprises a first amplifier configured to control the gate voltage by amplifying a difference between a set voltage and the drain voltage of the selected MOS transistor.

14. The threshold voltage measuring device of claim 13 , wherein the constant current supply circuit comprises:
a reference current source configured to generate a reference current that has a substantially constant magnitude; and
a current replication circuit configured to copy the reference current and provide a current that causes the drain-source current to flow through the selected MOS transistor.

15. The threshold voltage measuring device of claim 14 , wherein the reference current has a magnitude that is substantially equal to that of the drain-source current.

16. The threshold voltage measuring device of claim 14 , wherein the current replication circuit comprises:
a regulator configured to regulate a supply voltage according to a feedback voltage and output a rectified voltage;
a first resistor coupled between an output of the regulator and a drain of the selected MOS transistor;
a second resistor having first and second terminals, the first terminal coupled to the reference current source, a first voltage at the first terminal corresponding to a reference voltage, a second voltage at the second terminal corresponding to the set voltage; and
a second amplifier configured to amplify a difference between the rectified voltage and the reference voltage and provide the feedback voltage to the regulator.

17. The threshold voltage measuring device of claim 9 , wherein the plurality of MOS transistors comprise N-channel metal-oxide-semiconductor (NMOS) transistors.

18. The threshold voltage measuring device of claim 17 , wherein the bias voltage is a negative voltage.

19. The threshold voltage measuring device of claim 9 , wherein the plurality of MOS transistors comprise P-channel metal-oxide-semiconductor (PMOS) transistors.

20. The threshold voltage measuring device of claim 19 , wherein the bias voltage is a positive voltage.

Assignees

• Sk Hynix Inc
• Univ Yonsei Iacf
• Univ Yonsei Iacf

Inventors

• An Youngjae
• Park Jung-Hyun
• KIM Kiryong
• Jung Seong-Ook
• YIM Hyucksang

Classifications

• G01R31/2621 Primary

  for testing field effect transistors, i.e. FET's · CPC title

• G01R31/06

  Physics · mapped topic