Serial bit stream regular expression with states

Patent metadata

Field	Value
Publication number	US-9989559-B2
Application number	US-201414501750-A
Country	US
Kind code	B2
Filing date	Sep 30, 2014
Priority date	Dec 4, 2009
Publication date	Jun 5, 2018
Grant date	Jun 5, 2018

Abstract

A test and measurement instrument includes a user interface and a controller. The controller is configured to receive a serial bit stream and apply a logic to the serial bit stream to identify states within the serial bit stream. The result of applying the logic to the serial bit stream is a combined state/bit stream. A regular expression can be applied to the combined state/bit stream: the regular expression can include state information. The controller is also configured to present output data through the user interface in response to the application of the regular expression to the combined state/bit stream.

First claim

What is claimed is:

1. A test and measurement instrument, comprising:
a user interface; and
a controller configured to:
receive a serial bit stream;
analyze the serial bit stream to identify, via state identification logic, states within the serial bit stream, wherein the state identification logic defines conditions associated with each of the states;
generate a combined state/bit stream from the serial bit stream based, at least in part, on the identified states;
apply a first regular expression, that includes first state information, to the combined state/bit stream to produce output data;
detect that the first regular expression fails to match the combined state/bit stream;
in response to the detection that the first regular expression fails to match the combined state/bit stream, apply a second regular expression, including second state information, to the combined state/bit stream to produce the output data; and
present the output data through the user interface in response to the application of the regular expression to the combined state/bit stream.

2. The test and measurement instrument of claim 1 , wherein the state identification logic includes a state regular expression that defines the conditions associated with one or more of the states within the bit stream.

3. The test and measurement instrument of claim 1 , wherein the state identification logic includes an external function that defines the conditions associated with one or more of the states within the bit stream.

4. The test and measurement instrument of claim 1 , wherein the combined state/bit stream is time ordered.

5. The test and measurement instrument of claim 1 , wherein the second regular expression comprises an interim regular expression and a subsequent regular expression, and wherein the controller is further configured to apply the interim regular expression to the combined state/bit stream to produce an interim result, and to apply the subsequent regular expression to the interim result to produce the output data.

6. The test and measurement instrument of claim 1 , wherein the first regular expression defines a first packet type and the second regular expression defines a second packet type.

7. A method, comprising:
receiving a serial bit stream;
analyzing the serial bit stream to identify, via state identifying logic, states within the serial bit stream, wherein the state identification logic defines conditions associated with each of the states;
generating a combined state/bit stream from the serial bit stream based, at least in part, on the identified states;
detecting that a first regular expression, that includes first state information, fails to match the combined state/bit stream;
in response to the detecting, applying a second regular expression, that includes second state information, to the combined state/bit stream to produce output data; and
outputting the output data for additional analysis in response to the application of the second regular expression to the combined state/bit stream.

8. The method of claim 7 , wherein the state identifying logic includes a state regular expression to identify one or more of the states within the serial bit stream.

9. The method of claim 7 , wherein the state identifying logic includes an external function to identify one or more of the states within the serial bit stream.

10. The method of claim 7 , wherein the combined state/bit stream is time ordered.

11. The method of claim 7 , wherein applying the second regular expression to the combined state/bit stream includes:
applying an interim regular expression to the combined state/bit stream to produce an interim result based on the interim regular expression; and
applying a subsequent regular expression to the interim result to produce the output data.

12. The method of claim 7 , wherein generating the combined state/bit stream from the serial bit stream comprises association or replacement of bits in the serial bit stream that were utilized to identify one of the states with a state symbol associated with the one of the states.

13. The method of claim 7 , wherein the first regular expression defines a first packet type and the second regular expression defines a second packet type.

14. One or more non-transitory computer-readable storage media having instructions stored thereon, which, when executed by a test and measurement instrument, cause the test and measurement instrument to:
analyze a serial bit stream to identify, via state identification logic, states within the serial bit stream, wherein the state identification logic defines conditions associated with each of the states;
generate a combined state/bit stream from the serial bit stream based, at least in part, on the identified states;
detect that a first regular expression, that includes first state information, fails to match the combined state/bit stream;
in response to the detecting, apply a second regular expression, that includes second state information, to the combined state/bit stream to produce output data; and
output the output data, in response to the application of the second regular expression to the combined state/bit stream, for additional analysis.

15. The one or more non-transitory computer-readable media of claim 14 , wherein the state identification logic includes a state regular expression and/or an external function.

16. The one or more non-transitory computer-readable media of claim 14 , wherein to generate the combined state/bit stream from the serial bit stream comprises association or replacement of bits in the serial bit stream that were utilized to identify one of the states with a state symbol associated with the one of the states.

17. The one or more non-transitory computer-readable media of claim 14 , wherein the combined state/bit stream is time ordered.

18. The one or more non-transitory computer-readable media of claim 14 , wherein to apply the second regular expression, the instructions cause the test and measurement system to: apply an interim regular expression to the combined state/bit stream to produce an interim result, and to apply one or more additional regular expressions to the interim result to produce the output data.

19. The one or more non-transitory computer-readable media of claim 14 , wherein the first regular expression defines a first packet type and the second regular expression defines a second packet type.

Assignees

• Tektronix Inc

Inventors

• Rule Keith D
• Tanous Edward F
• Feist James

Classifications

• G01R13/0254 Primary

  for triggering, synchronisation · CPC title