Hardware trigger generation from a declarative protocol description
US-10148547-B2 · Dec 4, 2018 · US
This page is not indexed by search engines while we improve data quality.
Feist James patents
Feist James is listed as an inventor on 6 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Feist James |
| Total patents | 6 |
| First publication | Feb 26, 2015 |
| Latest publication | Dec 4, 2018 |
Notable patents
Publications ranked by popularity score, then publication date.
Serial bit stream regular expression with states
US-9989559-B2 · Jun 5, 2018 · US
Deriving hardware acceleration of decoding from a declarative protocol description
US-9338076-B1 · May 10, 2016 · US
Deriving hardware acceleration of decoding from a declarative protocol description
US-2016119218-A1 · Apr 28, 2016 · US
Hardware trigger generation from a declarative protocol description
US-2016119217-A1 · Apr 28, 2016 · US
Serial bit stream regular expression with states
US-2015057978-A1 · Feb 26, 2015 · US
Recent patents
Latest publications not already listed above.
No data yet.
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Tektronix Inc | 6 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G01R31/31903 | 4 |
| G11C29/56 | 4 |
| G01R13/0254 | 2 |
| H04L43/10 | 2 |
| H04L43/18 | 2 |