Method of manufacturing a multilayer substrate structure for fine line
US-2015282333-A1 · Oct 1, 2015 · US
US9986640B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9986640-B2 |
| Application number | US-201514927237-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 29, 2015 |
| Priority date | Jan 27, 2015 |
| Publication date | May 29, 2018 |
| Grant date | May 29, 2018 |
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A coil component includes coil conductors having a multilayer structure including via pads, and vias connected between the via pads on the respective layers. Portions or overall regions of the via pads on two layers which are adjacent to each other overlap each other, and the vias in two layers which are connected to each other by the via pad formed therebetween are disposed in alternating positions.
Opening claim text (preview).
What is claimed is: 1. A coil component comprising: a plurality of conductive patterns embedded in a plurality of insulating layers and stacked on each other, each conductive pattern including a coil conductor and a via pad; and a plurality of vias connecting the via pads embedded in the plurality of insulating layers, wherein portions or overall regions of the via pads embedded in two immediately adjacent insulating layers among the plurality of insulating layers overlap each other in a direction along which the plurality of conductive patterns are stacked on each other, the vias are alternately disposed, and a coil conductor and a via pad that are both embedded in one of the plurality of insulating layers are spaced-apart from each other. 2. The coil component of claim 1 , wherein the plurality of vias are positioned on different vertical lines parallel to the direction along which the plurality of conductive patterns are stacked. 3. The coil component of claim 1 , wherein longitudinal ends of the plurality of vias and longitudinal ends of the via pads are positioned on a common line parallel to the direction along which the plurality of conductive patterns are stacked. 4. The coil component of claim 1 , wherein a width of the via is a half a width of the via pad. 5. The coil component of claim 1 , wherein the plurality of insulating layers are disposed on a base substrate. 6. The coil component of claim 5 , wherein the base substrate is provided as a ferrite sintered body. 7. The coil component of claim 1 , wherein a pair of the vias disposed on opposite sides of the via pad embedded in the one of the plurality of insulating layers are in contact with the via pad embedded in the one of the plurality of insulating layers. 8. A coil component comprising: a plurality of conductive patterns embedded in a plurality of insulating layers and stacked on each other, each conductive pattern including a coil conductor and a via pad; and a plurality of vias connected between the via pads embedded in the plurality of insulating layers, wherein portions or overall regions of the via pads embedded in two immediately adjacent insulating layers among the plurality of insulating layers overlap each other, the vias are alternately disposed, the vias disposed in even insulating layers or the vias disposed in odd insulating layers are positioned on a common vertical line parallel to a direction along which the plurality of conductive patterns are stacked, and a coil conductor and a via pad that are both embedded in one of the plurality of insulating layers are spaced-apart from each other. 9. The coil component of claim 8 , wherein longitudinal ends of the vias and longitudinal ends of the via pads are positioned on a common line parallel to the direction along which the plurality of conductive patterns are stacked. 10. The coil component of claim 8 , wherein a width of the via is a half a width of the via pad. 11. The coil component of claim 8 , wherein the plurality of insulating layers are disposed on a base substrate. 12. The coil component of claim 11 , wherein the base substrate is provided as a ferrite sintered body. 13. The coil component of claim 8 , wherein a pair of the vias disposed on opposite sides of the via pad embedded in the one of the plurality of insulating layers are in contact with the via pad embedded in the one of the plurality of insulating layers. 14. A method of manufacturing a coil component, the method comprising: forming a first coil conductor and a first via pad on a first insulating layer, and forming a second insulating layer covering the first coil conductor and the first via pad on the first insulating layer; forming a second coil conductor and a second via pad which is interconnected to the first via pad through a first via formed on the first via pad and which partially or wholly overlaps the first via pad, on the second insulating layer; forming a third insulating layer covering the second coil conductor and the second via pad, on the second insulating layer, and forming a via hole which does not overlap the via formed on the first via pad to expose a portion of the second via pad; and forming a third coil conductor and a third via pad which is interconnected to the second via pad through a second via formed in the via hole by plating and which partially or wholly overlaps the second via pad, and forming a fourth insulating layer covering the third coil conductor and the third via pad on the third insulating layer, wherein the second coil conductor and the second via pad are spaced-apart from each other, or the third coil conductor and the third via pad are spaced-apart from each other. 15. The method of claim 14 , wherein the forming of the third coil conductor and the third via pad comprises: forming a seed layer on the third insulating layer and on an inner wall of the via hole, patterning a resist layer after attaching the resist layer onto the seed layer, growing a metal between patterns of the patterned resist, and etching the seed layer externally exposed after removing the resist. 16. The method of claim 14 , wherein the first insulating layer is formed on a base substrate before the forming of the first coil conductor and the first via pad, and the first coil conductor and the first via pad are formed on the first insulating layer. 17. The method of claim 14 , wherein the first via and the second via are formed on opposite sides of the second via pad, are in contact with the second via pad, and are not aligned to each other in a direction along which the first, second, and third coil conductors are stacked on each other.
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