Resistive switching memory stack for three-dimensional structure

Patent metadata

Field	Value
Publication number	US-9985206-B1
Application number	US-201715421659-A
Country	US
Kind code	B1
Filing date	Feb 1, 2017
Priority date	Feb 1, 2017
Publication date	May 29, 2018
Grant date	May 29, 2018

Abstract

A resistive switching memory stack is provided. The resistive switching memory stack includes a bottom electrode, formed from one or more metals. The resistive switching memory stack further includes a metal oxide layer, disposed over the bottom electrode, formed from an Atomic Layer Deposition (ALD) of one or more metal oxides. The resistive switching memory stack also includes a top electrode, disposed over the metal oxide layer, formed from the ALD of a plurality of metals into a metal layer stack. An oxygen vacancy concentration of the resistive switching memory stack is controlled by (i) a thickness of the plurality of metals forming the top electrode and (ii) a percentage of a particular one of the plurality of metals in the metal layer stack of the top electrode.

First claim

The invention claimed is:

1. A resistive switching memory stack, comprising:
a bottom electrode, formed from one or more metals;
a metal oxide layer, disposed over the bottom electrode, formed from an Atomic Layer Deposition (ALD) of one or more metal oxides; and
a top electrode, disposed over the metal oxide layer, formed from the ALD of a plurality of metals into a metal layer stack,
wherein a thickness of the plurality of metals forming the top electrode is configured to control an oxygen vacancy concentration of the resistive switching memory stack, wherein the top electrode includes a bottom layer, an intermediate layer, and a top layer, and wherein the bottom layer is formed from TiN,
wherein the intermediate layer is formed from (M)AlC, where M is a transition metal selected from the group consisting of Ti, Ta, and Nb.

2. The resistive switching memory stack of claim 1 , wherein the bottom electrode is formed from TiN.

3. The resistive switching memory stack of claim 1 , wherein the bottom electrode is 10-50 nm thick.

4. The resistive switching memory stack of claim 1 , wherein the metal oxide layer is formed from a compound selected from the group consisting of HfO 2 or Ta 2 O 5 or ZrO 2 .

5. The resistive switching memory stack of claim 1 , wherein the metal oxide layer is 3-10 nm thick.

6. The resistive switching memory stack of claim 1 , wherein the bottom layer is 0.3-3.0 nm thick.

7. The resistive switching memory stack of claim 1 , wherein the intermediate layer 132 is 1-5 nm thick.

8. The resistive switching memory stack of claim 1 , wherein the top layer is formed from TiN.

9. The resistive switching memory stack of claim 1 , wherein the top layer 133 is 10-50 nm thick.

10. The resistive switching memory stack of claim 1 , wherein the intermediate layer is formed from (M)AlC, the top layer is formed from TiN.

11. The resistive switching memory stack of claim 1 , wherein the resistive switching memory stack is formed in a Vertical Restive Random Access Memory (VRRAM).

12. The resistive switching memory stack of claim 1 , wherein the resistive switching memory stack is formed in an item selected from the group consisting of a deep Trench in Front End of Line (FEOL), a cylinder trench in Back End of Line (BEOL), and a fin structure.

13. The resistive switching memory stack of claim 1 , further comprising at least one low resistivity metal layer formed from one or more low resistivity metals, wherein at least one of the at least one low resistivity layer is formed under the bottom electrode or over the top electrode.

14. The resistive switching memory stack of claim 13 , wherein the one or more low resistivity metals comprise W, Al, and Cu.

15. The resistive switching memory stack of claim 13 , wherein the at least one low resistivity metal layer comprises a first low resistivity metal layer formed under the bottom electrode, and a second low resistivity metal layer formed over the top electrode.

16. The resistive switching memory stack of claim 15 , wherein at least one of the one or more low resistivity metals in the first low resistivity metal layer is different than that in the second low resistivity metal layer.

17. A method for forming a resistive switching memory stack, the method comprising:
forming a bottom electrode from one or more metals;
forming a metal oxide layer, disposed over the bottom electrode, from and Atomic Layer Deposition (ALD) of one or more metal oxides; and
forming a top electrode, disposed over the metal oxide layer, from the ALD of a plurality of metals into a metal layer stack,
wherein a thickness of the plurality of metals forming the top electrode is configured to control an oxygen vacancy concentration of the resistive switching memory stack, wherein the top electrode includes a bottom layer, an intermediate layer, and a top layer, wherein the bottom layer is formed from TiN, and wherein the intermediate layer is formed from (M)AlC, where M is a transition metal selected from the group consisting of Ti, Ta, and Nb.

Assignees

• IBM

Inventors

• Ando Takashi
• Narayanan Vijay
• Rozen John

Classifications

• H01L45/1616

  Electricity · mapped topic

• H01L45/1253

  Electricity · mapped topic

• H01L45/146 Primary

  Electricity · mapped topic

• H01L45/085

  Electricity · mapped topic

• H01L27/2481

  Electricity · mapped topic