Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-9985204-B2
Application number	US-201715451961-A
Country	US
Kind code	B2
Filing date	Mar 7, 2017
Priority date	Jul 15, 2016
Publication date	May 29, 2018
Grant date	May 29, 2018

Abstract

A semiconductor memory device including first lines and second lines overlapping and intersecting each other, variable resistance memory elements disposed at intersections between the first lines and the second lines, and switching elements disposed between the variable resistance memory elements and the first lines. At least one of the switching elements includes first and second chalcogenide compound layers, and conductive nano-dots disposed between the first and second chalcogenide compound layers.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
first lines and second lines overlapping and intersecting each other;
variable resistance memory elements disposed at intersections between the first lines and the second lines; and
switching elements disposed between the variable resistance memory elements and the first lines,
wherein at least one of the switching elements comprises:
first and second chalcogenide compound layers; and
conductive nano-dots disposed between the first and second chalcogenide compound layers.

2. The semiconductor memory device of claim 1 , wherein the first and second chalcogenide compound layers comprise nitrogen, the first chalcogenide compound layer including a nitrogen concentration greater than a nitrogen concentration of the second chalcogenide compound layer.

3. The semiconductor memory device of claim 1 , wherein the first and second chalcogenide compound layers comprise an amorphous material.

4. The semiconductor memory device of claim 1 , wherein the first chalcogenide compound layer has a thickness less than a thickness of the second chalcogenide compound layer.

5. The semiconductor memory device of claim 1 , further comprising:
first electrodes disposed between the first lines and the switching elements;
second electrodes disposed between the second lines and the variable resistance memory elements; and
third electrodes disposed between the switching elements and the variable resistance memory elements.

6. The semiconductor memory device of claim 5 , wherein the conductive nano-dots are spaced apart from the first electrode and the third electrode.

7. The semiconductor memory device of claim 1 , wherein the first and second chalcogenide compound layers include tellurium (Te) or selenium (Se) and germanium (Ge), antimony (Sb), bismuth (Bi), aluminum (Al), lead (Pb), tin (Sn), silver (Ag), arsenic (As), sulfur (S), silicon (Si), indium (In), titanium (Ti), gallium (Ga), or phosphorus (P).

8. The semiconductor memory device of claim 1 , wherein the conductive nano-dots include tellurium (Te), arsenic (As), silver (Ag), ruthenium (Ru), titanium (Ti), tantalum (Ta), tungsten (W), aluminum (Al), silicon (Si), or germanium (Ge).

9. The semiconductor memory device of claim 1 , wherein the variable resistance memory elements include chalcogen compounds, perovskite compounds, transition metal oxides, ferromagnetic materials, or anti-ferromagnetic materials.

10. A semiconductor memory device, comprising:
first lines and second lines overlapping and intersecting each other;
variable resistance memory elements disposed at intersections between the first lines and the second lines; and
threshold switching elements disposed between the variable resistance memory elements and the first lines,
wherein the threshold switching elements include conductive nano-dots, and
wherein the conductive nano-dots are spaced apart from a pair of electrodes.

11. The semiconductor memory device of claim 10 , wherein
at least one of the threshold switching elements is disposed between the electrodes.

12. The semiconductor memory device of claim 10 , wherein
the threshold switching elements comprise a chalcogenide compound, and
the conductive nano-dots comprise an element of the chalcogenide compound.

13. The semiconductor memory device of claim 12 , wherein
the chalcogenide compound includes tellurium (Te) or selenium (Se) and germanium (Ge), antimony (Sb), bismuth (Bi), aluminum (Al), lead (Pb), tin (Sn), silver (Ag), arsenic (As), sulfur (S), silicon (Si), indium (In), titanium (Ti), gallium (Ga), or phosphorus (P), and
the conductive nano-dots comprise tellurium (Te) nano-dots.

14. The semiconductor memory device of claim 10 , wherein
at least one of the threshold switching elements comprises first and second chalcogenide compound layers that are sequentially stacked, and
the conductive nano-dots are positioned at an interface between the first and second chalcogenide compound layers.

15. The semiconductor memory device of claim 14 , wherein the first and second chalcogenide compound layers comprise nitrogen, the first chalcogenide compound layer including a nitrogen concentration greater than a nitrogen concentration of the second chalcogenide compound layer.

16. A semiconductor memory device, comprising:
first lines and second lines overlapping and intersecting each other, wherein the second lines are disposed above the first lines;
variable resistance memory elements disposed at intersections between the first lines and the second lines; and
switching elements disposed between the variable resistance memory elements and the first lines,
wherein at least one of the switching elements comprises:
first, second, and third chalcogenide compound layers;
first conductive nano-dots disposed between the first and second chalcogenide compound layers; and
second conductive nano-dots disposed between the second and third chalcogenide compound layers.

17. The semiconductor memory device of claim 16 , wherein the first to third chalcogenide compound layers comprise nitrogen, the first and second chalcogenide compound layers including a nitrogen concentration greater than a nitrogen concentration of the third chalcogenide compound layer.

18. The semiconductor memory device of claim 17 , wherein the first and second chalcogenide compound layers have a nitrogen concentration in a range of from about 3.0% to about 5.0%, and the third chalcogenide compound layer has a nitrogen concentration in a range of from about 1.0% to about 2.0%.

19. The semiconductor memory device of claim 16 , wherein a thickness of the third chalcogenide compound layer is greater than a thickness of the first and second chalcogenide compound layers.

20. The semiconductor memory device of claim 16 , wherein the first and second conductive nano-dots comprise tellurium (Te) nano-dots.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Jinwoo
• Park Jeonghee
• Ahn Dongho
• Wu Zhe
• Shin Heeju
• Lee Ja Bin

Classifications

• H01L45/06

  Electricity · mapped topic

• H01L45/141 Primary

  Electricity · mapped topic

• H01L45/145

  Electricity · mapped topic

• H01L45/16

  Electricity · mapped topic

• H01L45/1233

  Electricity · mapped topic