Formation and structure of post enhanced diodes for orientation control

Patent metadata

Field	Value
Publication number	US-9985190-B2
Application number	US-201615158556-A
Country	US
Kind code	B2
Filing date	May 18, 2016
Priority date	May 18, 2016
Publication date	May 29, 2018
Grant date	May 29, 2018

Abstract

Embodiments are related to systems and methods for fluidic assembly, and more particularly to diodes offering orientation control properties in a fluidic assembly system.

First claim

What is claimed is:

1. A method for manufacturing a post enhanced diode, the method comprising:
providing a diode stack structure including an n-doped semiconductor layer and a p-doped semiconductor layer; and
forming a post disposed over the diode stack structure, wherein forming the post disposed over the diode stack structure includes:
forming a post material disposed over the diode stack structure, wherein a thickness of the post material defines a height of the post;
forming a hard mask disposed over the post material to define a width of the post, wherein forming the hard mask includes:
depositing an etch stop layer overlying the post material;
depositing a hard mask layer over the etch stop layer;
depositing a masking layer overlying the hard mask layer;
patterning the masking layer to define a post shape and exposing regions of the hard mask;
etching the hard mask layer to expose regions of the etch stop; and
etching the etch stop to expose regions of the post material; and
etching the post material using the hard mask as a guide to define the post.

2. The method of claim 1 , the method further comprising:
forming a current spreading layer on the diode stack structure, wherein the current spreading layer is between the post and the diode stack structure.

3. The method of claim 2 , wherein forming the post comprises:
depositing conductive metal post material overlying the current spreading layer; and
forming the post as an electrical contact for the post enhanced diode.

4. The method of claim 2 , wherein forming the post comprises:
selectively plating a conductive metal post material overlying the current spreading layer; and
forming the post as an electrical contact for the post enhanced diode.

5. The method of claim 1 , wherein the diode stack structure is a light emitting diode stack structure having an anode and a cathode.

6. The method of claim 1 , wherein the post is made of Silicon Dioxide, and wherein the hard mask is made of amorphous Silicon.

7. The method of claim 1 , wherein the hard mask is a first hard mask, and wherein forming the post disposed over the diode stack structure further comprises:
forming a second hard mask encasing the post, wherein the second hard mask defines a width of a diode structure; and
etching the diode stack structure using the second hard mask as a guide to define the diode structure.

8. The method of claim 7 , wherein the post is made of a first material, wherein the first hard mask is made of a second material, and wherein the second hard mask is made of the first material.

9. The method of claim 7 , wherein the etch stop layer is a first etch stop layer, wherein the hard mask layer is a first hard mask layer, wherein the masking layer is a first masking layer, wherein the method further comprises forming a current spreading layer on the diode stack structure, wherein the current spreading layer is between the post and the diode stack structure; and wherein forming the second hard mask encasing the post comprises:
conformally depositing a second hard mask layer overlying the post and a portion of a top surface of the current spreading layer;
conformally depositing a second masking layer overlying the second hard mask layer;
patterning the second masking layer to define a shape of the diode structure;
etching the second hard mask layer, the current spreading layer, and the diode stack structure;
removing the second hard mask and the first hard mask to yield expose the post enhanced diode.

10. The method of claim 9 , wherein the diode stack structure is attached to a substrate, the method further comprising:
separating the post enhanced diode from the substrate.

11. The method of claim 10 , the method further comprising:
forming at least one electrical contact on an exposed portion of the current spreading layer prior to separating the post enhanced diode from the substrate.

12. The method of claim 9 , wherein the first hard mask and the second hard mask are made of a material selected from a group consisting of: tetraethyl orthosilicate (TEOS), nickel, and chrome; wherein the first etch stop material is amorphous silicon, and wherein the post material is selected from a group consisting of: a dielectric film, TEOS, conductive metal, and silicon dioxide.

13. The method of claim 9 , wherein the shape of the diode structure is selected from a group consisting of: a circle, and a polygon.

14. The method of claim 1 , wherein a bottom layer of the diode stack structure opposite a top layer over which the post is disposed operates as an electrical contact.

15. The method of claim 1 , wherein the diode stack structure is formed on top of a substrate, the method further comprising:
forming a hard mask layer over a top surface of the diode stack structure;
conformally depositing a masking layer overlying the hard mask layer;
patterning the masking layer into plate shapes;
etching regions exposed by the hard mask layer down to the substrate to form a diode structure attached to the substrate; and
removing the hard mask layer.

16. The method of claim 15 , wherein the hard mask layer is a first hard mask layer, wherein the masking layer is a first masking layer, wherein forming the post disposed over the diode stack structure comprises:
subsequent to forming the diode structure, forming the post material over the diode structure; and
subsequent to forming the post, separating the post enhanced diode from the substrate.

17. The method of claim 16 , the method further comprising:
prior to separating the post enhanced diode from the substrate, forming at least one electrical contact on a top surface of the diode structure; and
separating the post enhanced diode from the substrate.

18. The method of claim 15 , wherein forming a hard mask layer over a top surface of the diode stack structure includes forming the hard mask layer on a current spreading layer disposed over the top surface of the diode stack structure, and wherein forming the post comprises:
depositing a conductive post material; and
forming the post as an electrical contact for the post enhanced diode.

19. A method for manufacturing a post enhanced diode, the method comprising:
providing a diode stack structure including an n-doped semiconductor layer and a p-doped semiconductor layer;
patterning and etching the diode stack structure to yield a diode structure;
forming a post disposed over the diode structure, wherein the post is formed subsequent to patterning and etching the diode stack structure, wherein a height of the diode stack is less than 3.5 times a height of the post; and
wherein forming the post disposed over the diode stack structure includes:
forming a post material disposed over the diode stack structure, wherein a thickness of the post material defines a height of the post;
forming a hard mask disposed over the post material to define a width of the post, wherein forming the hard mask includes:
depositing an etch stop layer overlying the post material;
depositing a hard mask layer over the etch stop layer;
depositing a masking layer overlying the hard mask layer;
patterning the masking layer to define a post shape and exposing regions of the hard mask;
etching the hard mask layer to expose regions of the etch stop; and
etching the etch stop to expose regions of the post material; and
etching the post material using the hard mask as a guide to define the post.

20. The method of claim 19 , wherein the diode stack structure i

Assignees

• Sharp Laboratories America Inc
• Elux Inc

Inventors

• Zhan Changqing
• Crowder Mark Albert
• Schuele Paul John

Classifications

• H10W72/071

  Connecting or disconnecting · CPC title

• H10W72/0198

  batch processes · CPC title

• H01L2933/0066

  Electricity · mapped topic

• H01L33/06

  Electricity · mapped topic

• H01L33/62 Primary

  Electricity · mapped topic