LED panel

US9985175B1 · US · B1

Patent metadata
FieldValue
Publication numberUS-9985175-B1
Application numberUS-201715857544-A
CountryUS
Kind codeB1
Filing dateDec 28, 2017
Priority dateJun 27, 2017
Publication dateMay 29, 2018
Grant dateMay 29, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An LED panel is disclosed. The LED panel includes LED chips and a mount substrate on which the LED chips are mounted by flip bonding. Each of the LED chips includes a sapphire substrate, a plurality of light emitting cells disposed below the sapphire substrate, and an etched portion formed between the plurality of light emitting cells. Each of the LED chips includes a plurality of color cells formed corresponding to the plurality of light emitting cells on the sapphire substrate to change or maintain the color of light from the corresponding light emitting cells and a plurality of light collecting portions formed corresponding to the plurality of light emitting cells and the plurality of color cells on the bottom surface of the substrate and adapted to collect light from the corresponding light emitting cells on the corresponding color cells.

First claim

Opening claim text (preview).

What is claimed is: 1. An LED panel comprising: LED chips, each of which comprises a sapphire substrate, a plurality of light emitting cells disposed below the sapphire substrate, and an etched portion formed between the plurality of light emitting cells; and a mount substrate on which the LED chips are mounted by flip bonding, wherein each of the LED chip comprises a plurality of color cells formed corresponding to the plurality of light emitting cells on the sapphire substrate to change or maintain the color of light from the corresponding light emitting cells and a plurality of light collecting portions formed corresponding to the plurality of light emitting cells and the plurality of color cells on the bottom surface of the substrate and adapted to collect light from the corresponding light emitting cells on the corresponding color cells. 2. The LED panel according to claim 1 , wherein each of the plurality of light collecting portions comprises a reflection plane formed in an area of the bottom surface of the overlying sapphire substrate vertically corresponding to the etched portion. 3. The LED panel according to claim 2 , wherein the reflection plane is gradually flared along the thickness direction of the sapphire substrate from the bottom surface of the sapphire substrate. 4. The LED panel according to claim 2 , wherein the reflection plane is gradually tapered along the thickness direction of the sapphire substrate from the bottom surface of the sapphire substrate. 5. The LED panel according to claim 1 , wherein each of the plurality of light collecting portions comprises a lens profile formed in an area of the bottom surface of the overlying sapphire substrate vertically corresponding to the corresponding light emitting cell to collect light from the light emitting cell on the corresponding color cell. 6. The LED panel according to claim 5 , wherein the lens profile is formed by patterning the bottom surface of the sapphire substrate. 7. The LED panel according to claim 6 , wherein the lens profile further comprises a portion of a gallium nitride epilayer grown on the pattern. 8. The LED panel according to claim 6 , wherein the lens profile further comprises a low refractive index material previously filled in the pattern before a gallium nitride epilayer is formed on the bottom surface of the sapphire substrate. 9. The LED panel according to claim 1 , wherein each of the plurality of light collecting portions comprises a lens profile formed in an area of the bottom surface of the overlying sapphire substrate vertically corresponding to the corresponding light emitting cell and a reflection plane formed in an area of the bottom surface of the overlying sapphire substrate vertically corresponding to the etched portion. 10. The LED panel according to claim 1 , wherein the plurality of color cells comprise groups of a first color cell, a second color cell, and a third color cell arranged adjacent to one another. 11. The LED panel according to claim 10 , wherein two or more of the first color cell, the second color cell, and the third color cell convert the wavelengths of light from the corresponding light emitting cells to output light of different colors. 12. The LED panel according to claim 10 , wherein the plurality of light emitting cells comprise a first light emitting cell, a second light emitting cell, and a third light emitting cell corresponding to the first color cell, the second color cell, and the third color cell, respectively, and emitting light of the same color; the first color cell receives light from the first light emitting cell, converts the received light into light of a first color, and emits the converted light; the second color cell receives light from the second light emitting cell, converts the received light into light of a second color different from the first color, and emits the converted light; and the third color cell receives light from the third light emitting cell and emits light of the same color. 13. The LED panel according to claim 1 , wherein the LED chip further comprises a light shielding layer formed to cover the lateral sides of the plurality of color cells. 14. The LED panel according to claim 1 , wherein the LED chip further comprises a passivation layer formed to cover the lateral sides of the plurality of light emitting cells. 15. The LED panel according to claim 14 , wherein the passivation layer comprises a reflective material adapted to send light from the light emitting cells upward. 16. The LED panel according to claim 1 , wherein the sapphire substrate is cut for thickness reduction. 17. The LED panel according to claim 1 , wherein the LED chip comprises an edge area surrounding the plurality of light emitting cells and an n-type area comprising the surface of an n-type semiconductor layer between the neighboring light emitting cells; and each of the plurality of light emitting cells comprises an active layer and a p-type semiconductor layer sequentially formed on the bottom surface of the n-type semiconductor layer. 18. The LED panel according to claim 17 , wherein the LED chip comprises a plurality of individual electrode pads individually connected to the p-type semiconductor layers of the plurality of light emitting cells and a common electrode pad connected to the n-type area and connected in common to the n-type semiconductor layer. 19. The LED panel according to claim 18 , wherein the mount substrate comprises a plurality of CMOS cells corresponding to the plurality of light emitting cells, a plurality of first electrodes corresponding to the plurality of individual electrode pads, and a second electrode corresponding to the common electrode pad; and a plurality of solder materials connect between the plurality of individual electrode pads and the plurality of first electrodes and between the common electrode pad and the second electrode.

Assignees

Inventors

Classifications

  • Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

  • H01L33/08Primary

    Electricity · mapped topic

  • Electricity · mapped topic

  • Electricity · mapped topic

  • Electricity · mapped topic

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Frequently asked questions

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What does patent US9985175B1 cover?
An LED panel is disclosed. The LED panel includes LED chips and a mount substrate on which the LED chips are mounted by flip bonding. Each of the LED chips includes a sapphire substrate, a plurality of light emitting cells disposed below the sapphire substrate, and an etched portion formed between the plurality of light emitting cells. Each of the LED chips includes a plurality of color cells f…
Who is the assignee on this patent?
Lumens Co Ltd
What technology area does this patent fall under?
Primary CPC classification H01L33/08. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue May 29 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).