FinFET varactor

Patent metadata

Field	Value
Publication number	US-9985144-B2
Application number	US-201715400201-A
Country	US
Kind code	B2
Filing date	Jan 6, 2017
Priority date	Jul 1, 2016
Publication date	May 29, 2018
Grant date	May 29, 2018

Abstract

A varactor transistor includes a semiconductor fin having a first conductivity type, a plurality of gate structures separated from each other and surrounding a portion of the semiconductor fin. The plurality of gates structures include a dummy gate structure on an edge of the semiconductor fin, and a first gate structure spaced apart from the dummy gate structure. The dummy gate structure and the gate structure each include a gate insulator layer on a surface portion of the semiconductor fin, a gate on the gate insulator layer, and a spacer on the gate. The varactor transistor also includes a raised source/drain region on the semiconductor fin and between the dummy gate structure and the first gate structure, the raised source/drain region and the gate of the dummy gate structure being electrically connected to a same potential.

First claim

What is claimed is:

1. A varactor transistor, comprising:
a semiconductor fin having a first conductivity type;
a plurality of gate structures separated from each other and surrounding a portion of the semiconductor fin, the plurality of gates structures comprising a first dummy gate structure on a first edge of the semiconductor fin, a second dummy gate structure on a second edge of the semiconductor fin, and a first gate structure between the first and second dummy gate structures and spaced apart from the first and second dummy gate structures, the first and second dummy gate structures and the gate structure each comprising a gate insulator layer on a surface portion of the semiconductor fin, a gate on the gate insulator layer, and a spacer on the gate;
a source disposed between the first dummy gate structure and the first gate structure;
a drain disposed between the second dummy gate structure and the first gate structure;
a source contact connected to the source and a drain contact connected to the drain; and
a first dummy gate contact connected to the gate of the first dummy gate structure and a second dummy gate contact connected to the gate of the second dummy gate structure,
wherein the source contact, drain contact, first dummy gate contact, and second dummy gate contact are connected to each other.

2. The varactor transistor of claim 1 , further comprising a substrate having a second conductivity type different from the first conductivity type, the semiconductor fin on the substrate and a reverse pn junction formed between the semiconductor fin and the substrate.

3. The varactor transistor of claim 1 , wherein the source contact, drain contact, first dummy gate contact and second dummy gate contact are connected to ground.

4. The varactor transistor of claim 1 , further comprising a trench isolation structure around the semiconductor fin and comprising a trench adjacent to the semiconductor fin and a first insulating layer in the trench.

5. The varactor transistor of claim 4 , further comprising an interlayer dielectric layer surrounding the plurality of gate structures and a portion of the source contact and a portion of the drain contact on the first insulator layer.

6. The varactor transistor of claim 5 , further comprising a first dielectric layer surrounding the first dummy gate contact, a portion of the first source contact and a portion of the first drain contact,
wherein the first dielectric layer exposes an upper surface of the first dummy gate contact, the second dummy gate contact, the source contact, and the drain contact.

7. The varactor transistor of claim 6 , further comprising a metal connector on the first dielectric layer and in contact with the first dummy gate contact, the second dummy gate contact, the source contact, and the drain contact.

8. The varactor transistor of claim 4 , further comprising an initial insulator layer between the interlayer dielectric layer and the semiconductor fin.

9. The varactor transistor of claim 1 , wherein the gate insulator layer comprises an interface layer on a surface portion of the semiconductor fin and a high-k dielectric layer on the interface layer.

10. The varactor transistor of claim 9 , wherein the gate comprising a work function adjusting layer on the high-k dielectric layer on the interface layer and a conductive material layer on the work function adjusting layer.

11. The varactor transistor of claim 1 , wherein the source and the drain each are disposed in a raised source region and in a raised drain region, respectively.

12. The varactor transistor of claim 7 , wherein the metal connector connects the first dummy gate contact, the second dummy gate contact, the source contact, and the drain contact to ground.

13. The varactor transistor of claim 7 , wherein the metal connector comprises copper, tungsten, or aluminum.

Assignees

• Semiconductor Mfg Int Shanghai Corp
• Semiconductor Mfg Int Beijing Corp

Inventors

• Zhou Fei

Classifications

• H10W20/0698

  Local interconnections · CPC title

• H01L29/0649

  Electricity · mapped topic

• H01L21/823437

  Electricity · mapped topic

• H01L29/0847

  Electricity · mapped topic

• H01L29/66795

  Electricity · mapped topic