Semiconductor wafer and method for processing a semiconductor wafer

Patent metadata

Field	Value
Publication number	US-9984915-B2
Application number	US-201414291107-A
Country	US
Kind code	B2
Filing date	May 30, 2014
Priority date	May 30, 2014
Publication date	May 29, 2018
Grant date	May 29, 2018

Abstract

According to various embodiments, a semiconductor wafer may include: a semiconductor body including an integrated circuit structure; and at least one tetrahedral amorphous carbon layer formed at least one of over or in the integrated circuit structure, the at least one tetrahedral amorphous carbon layer may include a substance amount fraction of sp 3 -hybridized carbon of larger than approximately 0.4 and a substance amount fraction of hydrogen smaller than approximately 0.1.

First claim

What is claimed is:

1. A method for processing a semiconductor wafer, the method comprising:
forming an integrated circuit structure in a semiconductor body;
forming at least one tetrahedral amorphous carbon layer at least one of over or in the integrated circuit structure by means of highly ionized sputtering, wherein the highly ionized sputtering is configured such that the at least one tetrahedral amorphous carbon layer comprises a substance amount fraction of sp3 hybridized carbon of larger than 0.4 and a substance amount fraction of hydrogen smaller than 0.1; and
forming at least one additional layer over the at least one tetrahedral amorphous carbon layer and performing a chemical mechanical polishing at least partially removing the additional layer exposing the at least one tetrahedral amorphous carbon layer at least partially.

2. The method according to claim 1 , further comprising:
forming an electronic structure at least one of over or in the semiconductor wafer.

3. The method of claim 1 ,
wherein the highly ionized sputtering comprises sputtering carbon atoms with an average ion energy in the range from about 40 eV per ion to about 5 keV per ion.

4. The method of claim 1 , wherein the highly ionized sputtering is performed using a high-power impulse magnetron sputtering process.

5. The method of claim 1 , wherein the at least one tetrahedral amorphous carbon layer is directly on the integrated circuit structure.

6. A method for processing a semiconductor wafer, the method comprising:
forming an integrated circuit structure in a semiconductor body;
forming at least one tetrahedral amorphous carbon layer at least one of over or in the integrated circuit structure by means of highly ionized sputtering, wherein the highly ionized sputtering is configured such that the at least one tetrahedral amorphous carbon layer comprises a substance amount fraction of sp3 hybridized carbon of larger than 0.4 and a substance amount fraction of hydrogen smaller than 0.1; and
forming at least one additional amorphous carbon layer at least one of over or in the integrated circuit structure by means of highly ionized sputtering, wherein at least one of a substance amount fraction of sp3 hybridized carbon of the at least one additional amorphous carbon layer or a substance amount fraction of hydrogen of the at least one additional amorphous carbon layer is different from the at least one tetrahedral amorphous carbon layer.

7. The method according to claim 6 ,
wherein the at least one additional amorphous carbon layer and the at least one tetrahedral amorphous carbon layer are formed via the very same sputtering system.

8. The method according to claim 7 ,
wherein the at least one tetrahedral amorphous carbon layer is formed under vacuum conditions in a first hydrogen partial pressure and the at least one additional amorphous carbon layer is formed under vacuum conditions in a second hydrogen partial pressure different from the first hydrogen partial pressure.

9. A method for processing a semiconductor wafer, the method comprising:
forming an integrated circuit structure in a semiconductor body;
forming at least one tetrahedral amorphous carbon layer at least one of over or in the integrated circuit structure by means of highly ionized sputtering, wherein the highly ionized sputtering is configured such that the at least one tetrahedral amorphous carbon layer comprises a substance amount fraction of sp3 hybridized carbon of larger than 0.4 and a substance amount fraction of hydrogen smaller than 0.1; and
carrying out a thermal treatment of the semiconductor wafer at a temperature of larger than about 400° C.

Assignees

• Infineon Technologies Ag

Inventors

• Kuenle Matthias
• Schmidt Gerhard
• Sporn Martin
• Kahn Markus
• Steinbrenner Juergen
• Joshi Ravi

Classifications

• H10P14/3406

  Carbon, e.g. diamond-like carbon · CPC title

• H10P14/22

  using physical deposition, e.g. vacuum deposition or sputtering · CPC title

• H10W10/011 Primary

  of isolation regions comprising dielectric materials · CPC title

• H10W10/10 Primary

  Isolation regions comprising dielectric materials · CPC title

• H10P14/3454

  Amorphous · CPC title