Method for manufacturing a chip arrangement including a ceramic layer

Patent metadata

Field	Value
Publication number	US-9984897-B2
Application number	US-201615268674-A
Country	US
Kind code	B2
Filing date	Sep 19, 2016
Priority date	Jan 16, 2013
Publication date	May 29, 2018
Grant date	May 29, 2018

Abstract

A chip arrangement is provided, the chip arrangement, including a carrier; a first chip electrically connected to the carrier; a ceramic layer disposed over the carrier; and a second chip disposed over the ceramic layer; wherein the ceramic layer has a porosity in the range from about 3% to about 70%.

First claim

What is claimed is:

1. A method for manufacturing a chip arrangement, the method comprising:
electrically connecting a first chip to a carrier;
disposing a ceramic layer having a porosity in the range from 3% to 70% over the carrier by plasma-dust deposition;
disposing at least one electrically conductive layer over the ceramic layer by plasma-dust deposition;
sintering the chip arrangement to adhere the ceramic layer to the carrier and the at least one electrically conductive layer to the ceramic layer; and then
disposing a second chip over the at least one electrically conductive layer.

2. The method according to claim 1 , further comprising:
adhering the ceramic layer directly on the carrier via an adhesive material.

3. The method according to claim 1 ,
wherein the ceramic layer comprises an electrically insulating material.

4. The method according to claim 3 ,
wherein the ceramic layer further comprises a thermally conducting material.

5. The method according to claim 1 ,
wherein the ceramic layer comprises one or more particles with one or more spaces between the one or more particles.

6. The method according to claim 5 ,
wherein the one or more particles comprise at least one from the following group of materials, the group of materials consisting of: aluminum oxide, aluminum nitride, silicon dioxide, silicon nitride, silicon carbide, titanium dioxide, titanium nitride, zirconium dioxide, boron nitride, boron carbide.

7. The method according to claim 5 , further comprising:
disposing an electrically insulating material over the ceramic layer that penetrates or interdiffuses inside the ceramic layer to fill the one or more spaces between the one or more particles.

8. The method according to claim 1 ,
wherein the carrier comprises a lead frame, the lead frame comprising at least one from the following group of materials, the group of materials consisting of: copper, nickel, iron, silver, gold, palladium, phosphorous, copper alloy, nickel alloy, iron alloy, silver alloy, gold alloy, palladium alloy, phosphorous alloy.

9. The method according to claim 1 , further comprising:
disposing an encapsulation material over the carrier, wherein the encapsulation material at least partially surrounds the first chip and the second chip, and one or more lateral sides of the carrier.

10. The method according to claim 1 , further comprising:
electrically connecting the first chip to the carrier via an electrically conductive medium comprising at least one material from the following group of materials, the group consisting of: a solder, a soft solder, a diffusion solder, a paste, a nanopaste, an adhesive, an electrically conductive adhesive, a thermally conductive adhesive.

11. The method according to claim 1 ,
wherein the first chip comprises a power semiconductor chip.

12. The method according to claim 1 ,
wherein the second chip comprises a semiconductor logic chip or a semiconductor memory chip.

13. The method according to claim 1 ,
wherein the sintering is at a temperature configured to prevent thermal load on the first chip connected to the carrier.

14. The method according to claim 1 ,
wherein the sintering is at a temperature in a range from 20° C. to 150° C.

15. A method for manufacturing a chip arrangement, the method comprising:
electrically connecting a first chip to a carrier;
disposing a ceramic pad on the carrier at a separation distance from the first chip;
disposing at least one electrically conductive layer over the ceramic pad;
sintering the chip arrangement to adhere the ceramic pad to the carrier and the at least one electrically conductive layer to the ceramic layer; and
disposing a second chip over the at least one electrically conductive layer.

16. The method of claim 15 , further comprising:
disposing at least one further electrically conductive layer directly over the carrier, wherein the ceramic pad is disposed over the at least one further electrically conductive layer and the sintering further adheres the at least one further electrically conductive layer to the carrier and the ceramic pad to the at least one further electrically conductive layer.

17. The method of claim 15 ,
wherein the ceramic layer comprises one or more particles with one or more spaces between the one or more particles and prior to disposing the at least one electrically conductive layer over the ceramic pad, the method further comprising: disposing an electrically insulating material over the ceramic layer that penetrates or interdiffuses inside the ceramic layer to fill the one or more spaces between the one or more particles.

18. The method of claim 15 ,
wherein the separation distance is in a range from 10 μm to 10 mm.

19. A method for manufacturing a chip arrangement, the method comprising:
electrically connecting a first chip to a carrier;
disposing at least one electrically conductive layer directly over the carrier by plasma-dust deposition before depositing a ceramic layer; then
disposing the ceramic layer having a porosity in the range from 3% to 70% directly over the at least one electrically conductive layer by plasma-dust deposition;
sintering the chip arrangement to adhere the at least one electrically conductive layer directly over the carrier and the ceramic layer to the carrier; and
disposing a second chip over the ceramic layer.

Assignees

• Infineon Technologies Ag

Inventors

• Mengel Manfred
• Mahler Joachim
• Hosseini Khalil
• Kalz Franz-Peter

Classifications

• H10D84/01

  Manufacture or treatment · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W90/752

  between stacked chips · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title