Voltage monitor for generating delay codes

Patent metadata

Field	Value
Publication number	US-9984732-B2
Application number	US-201715436234-A
Country	US
Kind code	B2
Filing date	Feb 17, 2017
Priority date	Apr 19, 2016
Publication date	May 29, 2018
Grant date	May 29, 2018

Abstract

Voltage monitors include a predelay cell having an input responsive to a first clock signal. This cell is configured to generate a predelayed clock signal at an output thereof. A serially-connected string of data delay cells is provided, which has an input responsive to the predelayed clock signal. A serially-connected string of clock delay cells is provided, which has an input responsive to a second clock signal that is synchronized to the first clock signal. A plurality latches are provided. The latches have respective data inputs, which are responsive to first periodic signals generated at respective outputs of the serially-connected string of data delay cells, and respective clock/sync terminals, which are responsive to second periodic signals generated at respective outputs of the serially-connected string of clock delay cells. The latches enable loading of a delay code value, which indicates power supply voltage variation.

First claim

What is claimed is:

1. A voltage monitor, comprising:
a predelay cell having an input terminal responsive to a first clock signal, said predelay cell configured to generate a predelayed clock signal, which is a delayed version of the first clock signal, at an output terminal thereof;
a serially-connected string of data delay cells having an input terminal responsive to the predelayed clock signal;
a serially-connected string of clock delay cells having an input terminal responsive to a second clock signal that is synchronized to the first clock signal; and
a plurality of latches having respective data input terminals, which are responsive to first periodic signals generated at respective output terminals of said serially-connected string of data delay cells, and respective clock input terminals, which are responsive to second periodic signals generated at respective output terminals of said serially-connected string of clock delay cells;
wherein the first periodic signals generated at respective output terminals of said serially-connected string of data delay cells are delayed versions of the predelayed clock signal.

2. The voltage monitor of claim 1 , wherein the second clock signal is in-phase with the first clock signal or the second clock signal is a delayed version of the first clock signal.

3. The voltage monitor of claim 1 , wherein said predelay cell comprises a serially-connected string of buffer cells that are equivalent to the data delay cells.

4. The voltage monitor of claim 1 , wherein the clock delay cells are configured as AND gates.

5. The voltage monitor of claim 1 , wherein said predelay cell is configured as a predelay selection circuit comprising a plurality of serially-connected strings of buffer cells and a corresponding plurality of multiplexers responsive to respective bits of a predelay selection code.

6. A voltage monitor comprising:
at least one predelay cell receiving a clock and having a first delay size;
data delay cells serially connected to a data path receiving an output of the at least one predelay cell, the data delay cells having a second delay size;
clock delay cells connected to a clock path receiving the clock, the clock delay cells having a third delay size; and
latch circuits configured to latch an output value of each of the data delay cells in response to a delay clock of each of the clock delay cells;
wherein the output value of each of the data delay cells corresponds to a respective delayed version of the clock provided to said at least one predelay cell; and
wherein said latch circuits are configured to latch the output value of each of the data delay cells in-sync with the delay clock.

7. The voltage monitor of claim 6 , wherein the at least one predelay cell and each of the data delay cells are implemented with the same buffer cell.

8. The voltage monitor of claim 6 , wherein the third delay size is greater than the second delay size.

9. The voltage monitor of claim 8 , wherein each of the data delay cells is implemented with a buffer cell, and
wherein each of the clock delay cells is implemented with an AND gate.

10. The voltage monitor of claim 6 , wherein output values latched to the latch circuit is a delay code, and
wherein the delay code corresponds to a value obtained by dividing the first delay size by a difference between the third delay size and the second delay size.

11. The voltage monitor of claim 6 , wherein each of the latch circuits is implemented with a flip-flop.

12. A voltage monitor comprising:
a predelay selection circuit connected to a data path receiving a clock and configured to select a predelay size in response to a predelay selection code;
a stage selection circuit configured to select at least one stage in response to a stage selection code to decide a size of delay associated with the data path;
a delay code generation circuit connected to the selected stage and configured to generate a delay code, the delay code generation circuit including serially connected data delay cells associated with the data path and clock delay cells serially connected to a clock path receiving the clock; and
latch circuits configured to latch an output value of each of the data delay cells in response to a clock delayed by each of the clock delay cells.

13. The voltage monitor of claim 12 , further comprising:
an internal clock generator configured to receive an external clock and to generate the clock in response to an enable signal.

14. The voltage monitor of claim 12 , wherein the predelay selection circuit comprises:
at least one predelay cell; and
at least one multiplexer configured to select one of an output value of the at least one predelay cell and a clock input to the data path in response to the predelay selection code.

15. The voltage monitor of claim 12 , wherein the predelay selection circuit comprises:
at least one predelay cell;
at least one first multiplexer configured to select one of an output value of the at least predelay cell and a clock input to the data path in response to the predelay selection code; and
at least one second multiplexer connected to the clock path in response to the predelay selection code.

16. The voltage monitor of claim 12 , wherein the stage selection circuit comprises:
a plurality of stages; and
a plurality of multiplexers configured to select at least one of the stages in response to the stage selection code, and
wherein each of the stages comprises:
at least one stage delay cell associated with the data path; and
at least one clock delay cell associated with the clock path.

17. The voltage monitor of claim 16 , wherein the number of delay cells included in each of the stages is a multiple of two.

18. The voltage monitor of claim 12 , further comprising:
second latch circuits configured to latch data stored in the latch circuits in response to another clock different from the clock.

19. The voltage monitor of claim 12 , wherein a delay size of each of the clock delay cells is greater than a delay size of each of the data delay cells.

20. The voltage monitor of claim 19 , wherein each of the clock delay cells is implemented with an AND gate.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Seomun Jun
• Shin Insub
• Do Kyungtae
• Choi Jungyun

Classifications

• G11C7/10

  Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers · CPC title

• G11C7/1012 Primary

  Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating · CPC title

• G11C7/222

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G11C5/143 Primary

  Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels (G11C5/148 takes precedence); Switching between alternative supplies (G11C5/141 takes precedence) · CPC title

• G01R19/16528

  using digital techniques or performing arithmetic operations (using digital techniques to measure a voltage or a current, see G01R19/25) · CPC title